| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 37 if (Mips::ACC64RegClass.contains(Src))
38 return std::make_pair((unsigned)Mips::PseudoMFHI,
39 (unsigned)Mips::PseudoMFLO);
41 if (Mips::ACC64DSPRegClass.contains(Src))
42 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
44 if (Mips::ACC128RegClass.contains(Src))
45 return std::make_pair((unsigned)Mips::PseudoMFHI64,
46 (unsigned)Mips::PseudoMFLO64);
89 case Mips::LOAD_CCOND_DSP
[all...] |
| /external/libunwind/include/ |
| libunwind-mips.h | 35 #ifdef mips
36 # undef mips macro
39 #define UNW_TARGET mips
50 /* FIXME for MIPS. Too big? What do other things use for similar tasks? */
53 /* The size of a "word" varies on MIPS. This type is used for memory
60 /* FIXME: MIPS ABIs. */
102 /* For MIPS, the CFA is the value of SP (r29) at the call site in the
122 #define UNW_TDEP_NUM_EH_REGS 2 /* FIXME for MIPS. */
131 MIPS. */
138 /* no mips-specific auxiliary proc-info *
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| dsp-r2.ll | 9 %3 = tail call i64 @llvm.mips.dpa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
13 declare i64 @llvm.mips.dpa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone
21 %3 = tail call i64 @llvm.mips.dps.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
25 declare i64 @llvm.mips.dps.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone
33 %3 = tail call i64 @llvm.mips.mulsa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
37 declare i64 @llvm.mips.mulsa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone
45 %3 = tail call i64 @llvm.mips.dpax.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
49 declare i64 @llvm.mips.dpax.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone
57 %3 = tail call i64 @llvm.mips.dpsx.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
61 declare i64 @llvm.mips.dpsx.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnon
[all...] |
| 2008-07-06-fadd64.ll | 1 ; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s
|
| 2008-07-07-FPExtend.ll | 1 ; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s
|
| 2008-08-04-Bitconvert.ll | 1 ; RUN: llc -march=mips < %s | FileCheck %s
|
| 2008-08-07-FPRound.ll | 1 ; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s
|
| 2008-08-08-ctlz.ll | 1 ; RUN: llc -march=mips < %s | FileCheck %s
|
| double2int.ll | 1 ; RUN: llc -march=mips < %s | FileCheck %s
|
| tls-alias.ll | 1 ; RUN: llc -march=mipsel -relocation-model=pic -disable-mips-delay-filler < %s | FileCheck %s
|
| weak.ll | 1 ; RUN: llc -march=mips < %s | FileCheck %s
|
| /build/core/combo/arch/mips/ |
| mips32-fp.mk | 1 # Configuration for Android on MIPS.
|
| mips32r2-fp.mk | 1 # Configuration for Android on MIPS.
|
| mips32r2dsp-fp.mk | 1 # Configuration for Android on MIPS.
|
| mips32r2dspr2-fp.mk | 1 # Configuration for Android on MIPS.
|
| mips32r6.mk | 1 # Configuration for Android on MIPS.
|
| /development/sys-img/ |
| images_mips_source.prop_template | 6 SystemImage.Abi=mips
|
| /device/generic/mini-emulator-mips/ |
| mini_emulator_mips.mk | 15 $(call inherit-product, device/generic/mips/mini_mips.mk)
20 PRODUCT_DEVICE := mini-emulator-mips
22 PRODUCT_MODEL := mini-emulator-mips
24 LOCAL_KERNEL := prebuilts/qemu-kernel/mips/kernel-qemu
|
| /external/chromium_org/third_party/libyuv/ |
| README.chromium | 12 Patch r1067 into r1038 to disable mips dsp2 code on iso r6.
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| nullvoid.ll | 1 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
|
| /external/llvm/test/MC/Mips/ |
| cpload.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ASM
3 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o -| \
4 # RUN: llvm-objdump -d -r -arch=mips - | \
8 # RUN: llvm-objdump -d -r -arch=mips - | \
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| abi-bad.s | 1 # RUN: not llvm-mc %s -triple mips-unknown-unknown -mcpu=mips64r2 2>&1 | FileCheck %s
|
| /external/lzma/CPP/7zip/ |
| Asm.mak | 4 !ELSEIF "$(CPU)" != "IA64" && "$(CPU)" != "MIPS"
|
| /external/qemu/target-mips/ |
| mips-defs.h | 33 /* MIPS ASEs. */
48 /* MIPS CPU defines. */
59 /* MIPS Technologies "Release 1" */
63 /* MIPS Technologies "Release 2" */
|
| /external/valgrind/main/memcheck/tests/ |
| test-plo-yes.vgtest | 1 prereq: test ! `../../tests/arch_test ppc32` && ! `../../tests/arch_test ppc64` && ! `../../tests/arch_test s390x` && ! `../../tests/mips_features mips-be`
|
