| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/third_party/libyuv/source/ |
| cpu_id.c | 63 // gcc -mfpu=neon defines __ARM_NEON__
64 // Enable Neon if you want support for Neon and Arm, and use MaskCpuFlags
65 // to disable Neon on devices that do not have it.
|
| /ndk/tests/device/b8708181-Vector4/jni/ |
| Android.mk | 7 LOCAL_CFLAGS += -DHAVE_NEON=1 -march=armv7-a -mfpu=neon -ftree-vectorize -ffast-math -mfloat-abi=softfp
|
| /external/llvm/test/CodeGen/ARM/ |
| vbsl.ll | 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
112 %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind
119 %vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind
126 %vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind
133 %vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
140 %vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind
147 %vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind
154 %vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind
161 %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
168 %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwin
[all...] |
| reg_sequence.ll | 27 %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
43 tail call void @llvm.arm.neon.vst1.v8i16(i8* %18, <8 x i16> %17, i32 1)
63 %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
66 %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7, i32 1) ; <<8 x i16>> [#uses=1]
70 tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9, i32 1)
73 tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10, i32 1)
84 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
91 tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1)
104 %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
107 %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2
[all...] |
| vsra.ll | 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
168 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
178 %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
188 %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
198 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
208 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
218 %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
228 %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
238 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
248 %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 (…)
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-neon-simd-shift.ll | 1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
336 %vqshrun = tail call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %b, i32 3)
347 %vqshrun = tail call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %b, i32 9)
359 %vqshrun = tail call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %b, i32 19)
369 %vrshrn = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %b, i32 3)
380 %vrshrn = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %b, i32 9)
392 %vrshrn = tail call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %b, i32 19)
402 %vqrshrun = tail call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %b, i32 3)
413 %vqrshrun = tail call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %b, i32 9)
425 %vqrshrun = tail call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %b, i32 19
[all...] |
| arm64-vcmp.ll | 1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
21 %tmp3 = call <2 x i32> @llvm.aarch64.neon.facge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
30 %tmp3 = call <4 x i32> @llvm.aarch64.neon.facge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
39 %tmp3 = call <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
43 declare <2 x i32> @llvm.aarch64.neon.facge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
44 declare <4 x i32> @llvm.aarch64.neon.facge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
45 declare <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone
52 %tmp3 = call <2 x i32> @llvm.aarch64.neon.facgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
61 %tmp3 = call <4 x i32> @llvm.aarch64.neon.facgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
70 %tmp3 = call <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2
[all...] |
| /external/chromium_org/third_party/skia/platform_tools/android/third_party/cpufeatures/ |
| cpu-features.h | 70 * instead of 16. Note that ARM mandates this feature is the 'NEON'
73 * NEON:
75 * NEON. Note that this mandates the VFP_D32 feature as well, per the
89 * Fused multiply-accumulate NEON instructions extension. Optional
130 * -mfpu=neon
132 * also support NEON intrinsics (see <arm_neon.h>).
133 * Generated code requires VFPv3|VFP_D32|NEON features.
141 * -mfpu=neon-vfpv4
142 * Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32|NEON|NEON_FMA
148 * NEON|NEON_FMA|IDIV_ARM|IDIV_THUMB
[all...] |
| /external/skia/platform_tools/android/third_party/cpufeatures/ |
| cpu-features.h | 70 * instead of 16. Note that ARM mandates this feature is the 'NEON'
73 * NEON:
75 * NEON. Note that this mandates the VFP_D32 feature as well, per the
89 * Fused multiply-accumulate NEON instructions extension. Optional
130 * -mfpu=neon
132 * also support NEON intrinsics (see <arm_neon.h>).
133 * Generated code requires VFPv3|VFP_D32|NEON features.
141 * -mfpu=neon-vfpv4
142 * Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32|NEON|NEON_FMA
148 * NEON|NEON_FMA|IDIV_ARM|IDIV_THUMB
[all...] |
| /ndk/sources/android/cpufeatures/ |
| cpu-features.h | 97 * instead of 16. Note that ARM mandates this feature is the 'NEON'
100 * NEON:
102 * NEON. Note that this mandates the VFP_D32 feature as well, per the
116 * Fused multiply-accumulate NEON instructions extension. Optional
157 * -mfpu=neon
159 * also support NEON intrinsics (see <arm_neon.h>).
160 * Generated code requires VFPv3|VFP_D32|NEON features.
168 * -mfpu=neon-vfpv4
169 * Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32|NEON|NEON_FMA
175 * NEON|NEON_FMA|IDIV_ARM|IDIV_THUMB
[all...] |
| /prebuilts/clang/linux-x86/host/3.5/bin/ |
| llvm-as | |
| llvm-dis | |
| llvm-link | |
| /frameworks/rs/driver/runtime/arch/ |
| neon.ll | 8 declare <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
9 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
10 declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
11 declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
12 declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
13 declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
14 declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
15 declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
17 declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
18 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnon
[all...] |
| asimd.ll | 8 declare <2 x float> @llvm.aarch64.neon.fmax.v2f32(<2 x float>, <2 x float>) nounwind readnone
9 declare <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float>, <4 x float>) nounwind readnone
10 declare <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
11 declare <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
12 declare <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
13 declare <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
14 declare <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
15 declare <4 x i16> @llvm.aarch64.neon.umax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
17 declare <2 x float> @llvm.aarch64.neon.fmin.v2f32(<2 x float>, <2 x float>) nounwind readnone
18 declare <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float>, <4 x float>) nounwind readnon
[all...] |
| /external/chromium_org/third_party/libvpx/ |
| libvpx_srcs_arm_neon_cpu_detect.gypi | 113 '<(libvpx_source)/vp8/encoder/arm/neon/fastquantizeb_neon.asm',
163 '<(libvpx_source)/vp9/common/arm/neon/vp9_avg_neon.asm',
164 '<(libvpx_source)/vp9/common/arm/neon/vp9_convolve8_avg_neon.asm',
165 '<(libvpx_source)/vp9/common/arm/neon/vp9_convolve8_neon.asm',
166 '<(libvpx_source)/vp9/common/arm/neon/vp9_copy_neon.asm',
167 '<(libvpx_source)/vp9/common/arm/neon/vp9_dc_only_idct_add_neon.asm',
168 '<(libvpx_source)/vp9/common/arm/neon/vp9_idct16x16_1_add_neon.asm',
169 '<(libvpx_source)/vp9/common/arm/neon/vp9_idct16x16_add_neon.asm',
170 '<(libvpx_source)/vp9/common/arm/neon/vp9_idct32x32_1_add_neon.asm',
171 '<(libvpx_source)/vp9/common/arm/neon/vp9_idct32x32_add_neon.asm'
[all...] |
| /external/chromium_org/build/config/ |
| arm.gni | 21 # Whether to use the neon FPU instruction set or not.
61 arm_fpu = "neon"
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/test/support/ |
| float_fft_armv7.c | 16 "Test forward and inverse floating-point FFT (Non-NEON)\n";
23 printf("Non-NEON tests finished.\n");
|
| float_fft_neon.c | 22 " (NEON)\n"
33 #define FINISHED_MESSAGE "NEON tests finished.\n"
|
| float_rfft_armv7.c | 17 "Test forward and inverse real floating-point FFT (Non-NEON)\n";
24 printf("Non-NEON tests finished.\n");
|
| float_rfft_neon.c | 17 "Test forward and inverse real floating-point FFT (NEON)\n";
24 printf("NEON tests finished.\n");
|
| /external/clang/include/clang/Basic/ |
| BuiltinsNEON.def | 1 //===--- BuiltinsNEON.def - NEON Builtin function database ------*- C++ -*-===//
10 // This file defines the NEON-specific builtin function database. Users of
|
| CMakeLists.txt | 37 # ARM NEON
38 clang_tablegen(arm_neon.inc -gen-arm-neon-sema
|
| /external/clang/test/CodeGen/ |
| arm64_vset_lane.c | 1 // RUN: %clang_cc1 -O1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -emit-llvm %s | FileCheck %s
23 // CHECK@ @llvm.aarch64.neon.smaxv.i32.v8i8
|
| /external/clang/test/CodeGenCXX/ |
| poly-unsigned.cpp | 1 // RUN: %clang_cc1 -triple arm64-apple-ios -target-feature +neon -ffreestanding -S -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-UNSIGNED-POLY %s
2 // RUN: %clang_cc1 -triple arm64-linux-gnu -target-feature +neon -ffreestanding -S -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-UNSIGNED-POLY %s
|
