| /bionic/libc/arch-arm/include/machine/ |
| endian.h | 36 /* According to RealView Assembler User's Guide, REV and REV16 are available
42 * REV16 Rd, Rm
49 __asm__ __volatile__("rev16 %0, %0" : "+l" (_x)); \
|
| /external/llvm/test/MC/ARM/ |
| thumb.s | 19 rev16 r3, r4
22 @ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| 2010-04-26-CopyRegCrash.ll | 54 %asmtmp.i.i179 = tail call i16 asm "rev16 $0, $1\0A", "=l,l"(i16 undef) nounwind ; <i16> [#uses=1]
55 %asmtmp.i.i178 = tail call i16 asm "rev16 $0, $1\0A", "=l,l"(i16 %asmtmp.i.i179) nounwind ; <i16> [#uses=1]
|
| /ndk/tests/build/issue17144-byteswap/ |
| build.sh | 26 grep -qw rev16 issue17144-byteswap.s
27 fail_panic "armeabi-v7a doesn't use rev16 instruction for __swap16()"
|
| /bionic/libc/arch-arm64/include/machine/ |
| endian.h | 39 __asm volatile ("rev16 %0, %0" : "+r" (_x)); \
|
| /development/ndk/platforms/android-L/arch-arm64/include/machine/ |
| endian.h | 39 __asm volatile ("rev16 %0, %0" : "+r" (_x)); \
|
| /prebuilts/ndk/9/platforms/android-21/arch-arm64/usr/include/machine/ |
| endian.h | 39 __asm volatile ("rev16 %0, %0" : "+r" (_x)); \
|
| /external/llvm/test/CodeGen/ARM/ |
| rev.ll | 5 ; CHECK: rev16 r0, r0
75 ; CHECK: rev16 r0, r0
119 ; CHECK: rev16 r0, r0
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-rev.ll | 25 ; CHECK: rev16 w0, w0
39 ; 64-bit REV16 is *not* a swap then a 16-bit rotation:
41 ; 01234567 ->(rev16) 10325476
45 ; CHECK-NOT: rev16 x0, x0
162 ;CHECK: rev16.8b
170 ;CHECK: rev16.16b
|
| dp1.ll | 44 ; CHECK: rev16 {{w[0-9]+}}, {{w[0-9]+}}
|
| arm64-big-endian-bitconverts.ll | 454 ; CHECK: rev16 v{{[0-9]+}}.8b
532 ; CHECK: rev16 v{{[0-9]+}}.8b
1013 ; CHECK: rev16 v{{[0-9]+}}.16b
1093 ; CHECK: rev16 v{{[0-9]+}}.16b
|
| /external/llvm/test/CodeGen/Thumb/ |
| rev.ll | 5 ; CHECK: rev16 r0, r0
|
| /external/valgrind/main/none/tests/arm/ |
| v6intARM.c | [all...] |
| v6intARM.stdout.exp | [all...] |
| /external/chromium_org/v8/src/arm64/ |
| constants-arm64.h | [all...] |
| disasm-arm64.cc | 581 FORMAT(REV16, "rev16");
[all...] |
| macro-assembler-arm64-inl.h | 1016 void MacroAssembler::Rev16(const Register& rd, const Register& rn) {
1019 rev16(rd, rn);
[all...] |
| /external/vixl/src/a64/ |
| constants-a64.h | 815 REV16 = DataProcessing1SourceFixed | 0x00000400,
816 REV16_w = REV16,
817 REV16_x = REV16 | SixtyFourBits,
[all...] |
| disasm-a64.cc | 588 FORMAT(REV16, "rev16");
[all...] |
| /external/vixl/doc/ |
| supported-instructions.md | 686 ### rev16 ###
690 void rev16(const Register& rd, const Register& rn)
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 104 REV16,
|
| AArch64SchedCyclone.td | 147 // CLS,CLZ,RBIT,REV,REV16,REV32
497 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-arithmetic.txt | 408 # CHECK: rev16 w1, w2
410 # CHECK: rev16 x1, x2
|
| /external/clang/test/CodeGen/ |
| aarch64-neon-misc.c | 454 // CHECK: rev16 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
460 // CHECK: rev16 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
466 // CHECK: rev16 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
472 // CHECK: rev16 v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
478 // CHECK: rev16 v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
484 // CHECK: rev16 v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
[all...] |
| /external/llvm/test/MC/AArch64/ |
| arm64-arithmetic-encoding.s | 440 rev16 w1, w2
441 rev16 x1, x2
|
