| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 74 switch ((Imm >> 6) & 0x7) {
119 return Imm & 0x7;
124 assert((Imm & 0x7) == Imm && "invalid immediate!");
139 return getExtendType((Imm >> 3) & 0x7);
172 assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
173 return (getExtendEncoding(ET) << 3) | (Imm & 0x7);
185 return getExtendType((Imm >> 1) & 0x7);
354 uint8_t Exp = (Imm >> 4) & 0x7;
390 Exp = ((Exp+3) & 0x7) ^ 4;
418 Exp = ((Exp+3) & 0x7) ^ 4
[all...] |
| /external/openssl/crypto/bn/asm/ |
| x86-gf2m.pl | 85 &mov (@i[0],0x7);
155 &mov (@i[0],0x7);
162 &mov (@i[1],0x7); # 5-byte instruction!?
167 &mov (@i[0],0x7);
172 &mov (@i[1],0x7);
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/9/platforms/android-19/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/mach-au1x00/ |
| au1000.h | 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20)
511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16)
735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
771 #define SYS_CS_MUX_FQ5 0x7
[all...] |
| /external/libvpx/libvpx/vp9/common/ |
| vp9_idct.c | 324 int x7 = input[6]; local
326 if (!(x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7)) {
339 s6 = cospi_26_64 * x6 + cospi_6_64 * x7;
340 s7 = cospi_6_64 * x6 - cospi_26_64 * x7;
349 x7 = dct_const_round_shift(s3 - s7);
358 s6 = -cospi_24_64 * x6 + cospi_8_64 * x7;
359 s7 = cospi_8_64 * x6 + cospi_24_64 * x7;
368 x7 = dct_const_round_shift(s5 - s7);
373 s6 = cospi_16_64 * (x6 + x7);
374 s7 = cospi_16_64 * (x6 - x7);
648 int x7 = input[6]; local
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/ |
| vp9_idct.c | 324 int x7 = input[6]; local
326 if (!(x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7)) {
339 s6 = cospi_26_64 * x6 + cospi_6_64 * x7;
340 s7 = cospi_6_64 * x6 - cospi_26_64 * x7;
349 x7 = dct_const_round_shift(s3 - s7);
358 s6 = -cospi_24_64 * x6 + cospi_8_64 * x7;
359 s7 = cospi_8_64 * x6 + cospi_24_64 * x7;
368 x7 = dct_const_round_shift(s5 - s7);
373 s6 = cospi_16_64 * (x6 + x7);
374 s7 = cospi_16_64 * (x6 - x7);
648 int x7 = input[6]; local
[all...] |
| /hardware/qcom/msm8960/kernel-headers/linux/mfd/ |
| timpani-audio.h | 82 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7
95 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7
385 #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7
395 #define TIMPANI_TXFE_CLT_RESERVED_M 0x7
[all...] |
| /hardware/qcom/msm8960/original-kernel-headers/linux/ |
| timpani-audio.h | 69 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7
80 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7
392 #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7
402 #define TIMPANI_TXFE_CLT_RESERVED_M 0x7
636 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7
824 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7
[all...] |
| /external/valgrind/main/none/tests/arm64/ |
| integer.c | [all...] |
| /external/libhevc/common/arm64/ |
| ihevc_inter_pred_filters_luma_vert_w16inp.s | 125 subs x7,x3,#0 //x3->ht
143 mul x7, x7, x3 //multiply height by width
144 sub x7, x7,#4 //subtract by one for epilog
222 subs x7,x7,#4
310 subs x7,x7,#4
|
| ihevc_inter_pred_luma_vert_w16inp_w16out.s | 134 subs x7,x3,#0 //r3->ht
154 mul x7, x7, x3 //multiply height by width
155 sub x7, x7, #4 //subtract by one for epilog
235 subs x7,x7,#4
328 subs x7,x7,#4
|
| ihevc_sao_band_offset_chroma.s | 59 //x7 => *pi1_sao_offset_u 52
89 mov x19,x7 // pi1_sao_offset_u 52
124 MOV x7, x19 //Loads pi1_sao_offset_u
140 LD1 {v30.8b},[x7] //pi1_sao_offset_u load
310 ADD x7,x6,x1
318 LD2 {v21.8b, v22.8b},[x7] //vld1q_u8(pu1_src_cpy)
348 ST2 {v21.8b, v22.8b},[x7] //vst1q_u8(pu1_src_cpy, au1_cur_row)
366 ADD x7,x6,x1
379 LD2 {v21.8b, v22.8b},[x7] //vld1q_u8(pu1_src_cpy)
416 ST1 {v21.8b},[x7] //vst1q_u8(pu1_src_cpy, au1_cur_row
[all...] |
| ihevc_inter_pred_chroma_horz.s | 122 mov x7,x16 //loads ht
126 subs x14,x7,#0 //checks for ht == 0
149 tst x7,#3
333 // mov x0, x7
474 mov x7,x5
510 subs x7,x7,#8 //decrement the wd loop
525 mov x7,x5
582 subs x7,x7,#8 //(prologue)decrement the wd loo
[all...] |
| ihevc_intra_pred_chroma_mode_3_to_9.s | 113 adrp x7, :got:gai4_ihevc_ang_table
114 ldr x7, [x7, #:got_lo12:gai4_ihevc_ang_table]
119 add x7, x7, x5, lsl #2 //gai4_ihevc_ang_table[mode]
120 ldr w7, [x7] //intra_pred_ang
121 sxtw x7,w7
135 sub x7, x5, #3
139 add x12, x12, x7, lsl #4
142 mov x7, #
[all...] |
| ihevc_weighted_pred_bi_default.s | 107 // x7 => lvl_shift2
132 mov x19,x7 // lvl_shift2 52
141 mov x7,x19 //load lvl_shift2
152 neg x7, x20
227 add x0,x0,x7 //pi2_src1 + 4*src_strd1 - 2*wd(since pi2_src1 is 16 bit pointer double the increment with double the wd decrement)
244 neg x7, x20
272 add x0,x0,x7 //pi2_src1 + 2*src_strd1 - 2*wd(since pi2_src1 is 16 bit pointer double the increment with double the wd decrement)
326 add x0,x0,x7 //pi2_src1 + 4*src_strd1 - 2*wd(since pi2_src1 is 16 bit pointer double the increment with double the wd decrement)
347 neg x7, x20
378 add x0,x0,x7 //pi2_src1 + 4*src_strd1 - 2*wd(since pi2_src1 is 16 bit pointer double the inc (…)
[all...] |
| /external/chromium_org/third_party/libvpx/source/libvpx/vp9/common/mips/dspr2/ |
| vp9_itrans16_dspr2.c | 924 int x7 = input[6]; local
[all...] |
