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    Searched refs:InstrItins (Results 26 - 35 of 35) sorted by null

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  /external/llvm/lib/Target/R600/
AMDGPUTargetMachine.cpp 80 InstrItins(&Subtarget.getInstrItineraryData()) {
  /external/llvm/lib/CodeGen/
MachineLICM.cpp 70 const InstrItineraryData *InstrItins;
333 InstrItins = TM->getInstrItineraryData();
    [all...]
PostRASchedulerList.cpp 198 const InstrItineraryData *InstrItins = TM.getInstrItineraryData();
200 TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
TwoAddressInstructionPass.cpp 74 const InstrItineraryData *InstrItins;
792 if (TII->getInstrLatency(InstrItins, MI) > 1)
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 51 InstrItins(mf.getTarget().getInstrItineraryData()) {}
608 if (!InstrItins || InstrItins->isEmpty()) {
622 SU->Latency += TII->getInstrLatency(InstrItins, N);
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
    [all...]
ResourcePriorityQueue.cpp 46 InstrItins(IS->getTargetLowering()->getTargetMachine().getInstrItineraryData())
322 if (Packet.size() >= InstrItins->SchedModel->IssueWidth) {
  /external/llvm/lib/Target/ARM/
ARMSubtarget.cpp 266 InstrItins = getInstrItineraryForCPU(CPUString);
  /external/llvm/lib/Target/Mips/
MipsSubtarget.cpp 198 InstrItins = getInstrItineraryForCPU(CPUName);
  /external/llvm/lib/Target/PowerPC/
PPCSubtarget.cpp 157 InstrItins = getInstrItineraryForCPU(CPUName);
  /external/llvm/lib/Target/X86/
X86Subtarget.cpp 225 InstrItins = getInstrItineraryForCPU(CPUName);

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