| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vs_emit.c | 108 struct prog_instruction *inst = vp->Base.Instructions + i;
255 struct prog_instruction *inst = &c->vp->program.Base.Instructions[i];
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_fragshader.c | 145 struct atifs_instruction *inst = &shader->Instructions[pass][pc];
281 /* fglrx does clamp the last instructions to 0_1 it seems */
|
| /external/mesa3d/src/mesa/swrast/ |
| s_atifragshader.c | 344 inst = &shader->Instructions[pass][pc];
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 0 # Instructions that are invalid
|
| invalid-mips5.s | 0 # Instructions that are invalid
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 0 # Instructions that are valid
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 0 # Instructions that are valid
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 0 # Instructions that are valid
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 0 # Instructions that are valid
|
| /external/oprofile/events/mips/24K/ |
| events | 15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
32 event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
33 event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
34 event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
35 event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
37 event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions complete
[all...] |
| /external/oprofile/events/mips/34K/ |
| events | 15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
32 event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
33 event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
34 event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
35 event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
37 event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions complete
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/main/ |
| mtypes.h | [all...] |
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/ |
| sse5-all.asm | 0 ; Instructions are ordered in SSE5 databook order
488 ; SSE5 instructions that are also SSE4.1 instructions
|
| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 6 # for fpu instructions
8 # FPU Instructions
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 0 # Instructions that are valid
|
| /external/mesa3d/src/mesa/main/ |
| mtypes.h | [all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
32 event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
33 event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
34 event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
35 event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
37 event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions complete
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow.c | 191 /* This function only works with normal instructions. */
224 /* This function only works with pair instructions. */
286 * \warning Does not report output registers for paired instructions!
330 * \warning Does not report output registers for paired instructions!
568 0 /*Pair Instructions don't use RelAddr*/,
614 * destination register have been overwritten by other instructions).
707 for(tmp = writer->Next; tmp != &d->C->Program.Instructions;
831 * by instructions 0 and 1.
|
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| prog_print.c | 880 /* XXX may need other special-case instructions */
956 indent = _mesa_fprint_instruction_opt(f, prog->Instructions + i,
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/ |
| st_mesa_to_tgsi.c | 112 * After we've emitted all instructions, we'll go over the list
139 * Allocate additional space for instructions if needed.
770 * Emit the TGSI instructions for inverting and adjusting WPOS.
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
392 SmallVector<MCInst, 8> Instructions;
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow.c | 191 /* This function only works with normal instructions. */
224 /* This function only works with pair instructions. */
286 * \warning Does not report output registers for paired instructions!
330 * \warning Does not report output registers for paired instructions!
568 0 /*Pair Instructions don't use RelAddr*/,
614 * destination register have been overwritten by other instructions).
707 for(tmp = writer->Next; tmp != &d->C->Program.Instructions;
831 * by instructions 0 and 1.
|
| /external/mesa3d/src/mesa/program/ |
| prog_print.c | 880 /* XXX may need other special-case instructions */
956 indent = _mesa_fprint_instruction_opt(f, prog->Instructions + i,
[all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_mesa_to_tgsi.c | 112 * After we've emitted all instructions, we'll go over the list
139 * Allocate additional space for instructions if needed.
770 * Emit the TGSI instructions for inverting and adjusting WPOS.
[all...] |
| /frameworks/compile/libbcc/lib/Renderscript/ |
| RSForEachExpand.cpp | 24 #include <llvm/IR/Instructions.h>
282 /// instructions can be added to the loop body.
|
