| /development/ndk/platforms/android-9/arch-mips/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /development/ndk/platforms/android-L/arch-mips/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /development/ndk/platforms/android-L/arch-mips64/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-19/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-21/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-21/arch-mips64/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /libcore/luni/src/test/java/libcore/java/lang/ |
| ClassCastExceptionTest.java | 81 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
86 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
|
| /external/lzma/C/ |
| Sha256.c | 25 #define S0(x) (rotrFixed(x, 2) ^ rotrFixed(x,13) ^ rotrFixed(x, 22))
27 #define s0(x) (rotrFixed(x, 7) ^ rotrFixed(x,18) ^ (x >> 3))
macro
31 #define blk2(i) (W[i&15] += s1(W[(i-2)&15]) + W[(i-7)&15] + s0(W[(i-15)&15]))
49 d += h; h += S0(a) + Maj(a, b, c)
64 d(i) += h(i); h(i) += S0(a(i)) + Maj(a(i), b(i), c(i))
142 #undef S0
144 #undef s0
macro
|
| /external/libgsm/src/ |
| long_term.c | 366 register float S0 = 0, S1 = 0, S2 = 0, S3 = 0, S4 = 0,
381 E = W * a; S0 += E; } else (a = lp[K])
407 if (S0 > L_max) { L_max = S0; Nc = lambda; }
532 register float S0 = 0, S1 = 0, S2 = 0, S3 = 0, S4 = 0,
547 E = W * a; S0 += E
573 if (S0 > L_max) { L_max = S0; Nc = lambda; }
746 register float S0 = 0, S1 = 0, S2 = 0, S3 = 0, S4 = 0,
761 E = W * a; S0 +=
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16FrameLowering.cpp | 77 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
96 .addReg(Mips::S0);
112 // Registers RA, S0,S1 are the callee saved registers and they
137 // Registers RA,S0,S1 are the callee saved registers and they will be restored
184 MF.getRegInfo().setPhysRegUsed(Mips::S0);
|
| Mips16RegisterInfo.cpp | 111 FrameReg = Mips::S0;
|
| /art/runtime/arch/arm64/ |
| registers_arm64.h | 154 S0 = 0,
|
| /art/compiler/jni/quick/arm64/ |
| calling_convention_arm64.cc | 37 S0, S1, S2, S3, S4, S5, S6, S7
51 return Arm64ManagedRegister::FromSRegister(S0);
108 int fp_reg_index = 0; // D0/S0.
|
| /bionic/libc/arch-mips/bionic/ |
| _setjmp.S | 58 REG_S s0, SC_REGS+S0*REGSZ(a0)
108 REG_L s0, SC_REGS+S0*REGSZ(a0)
|
| /bionic/libc/arch-mips64/bionic/ |
| _setjmp.S | 58 REG_S s0, SC_REGS+S0*REGSZ(a0)
108 REG_L s0, SC_REGS+S0*REGSZ(a0)
|
