/external/llvm/ |
Android.mk | 73 # X86 Code Generation Libraries 75 lib/Target/X86 \ 76 lib/Target/X86/AsmParser \ 77 lib/Target/X86/InstPrinter \ 78 lib/Target/X86/Disassembler \ 79 lib/Target/X86/MCTargetDesc \ 80 lib/Target/X86/TargetInfo \ 81 lib/Target/X86/Utils
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shared_llvm.mk | 82 # Host build pulls in all ARM, Mips, X86 components. 114 # Device build selectively pulls in ARM, Mips, X86 components.
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/external/llvm/lib/Target/X86/ |
Makefile | 1 ##===- lib/Target/X86/Makefile -----------------------------*- Makefile -*-===## 12 TARGET = X86
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X86InstrInfo.h | 1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// 10 // This file contains the X86 implementation of the TargetInstrInfo class. 29 namespace X86 { 30 // X86 specific condition code. These correspond to X86_*_COND in 54 // which can't be represented on x86 with a single condition. These 80 } // end namespace X86; 124 return Op+X86::AddrSegmentReg <= MI->getNumOperands() && 125 MI->getOperand(Op+X86::AddrBaseReg).isReg() && 126 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) && 127 MI->getOperand(Op+X86::AddrIndexReg).isReg() & [all...] |
X86VZeroUpper.cpp | 10 // This file defines the pass which inserts x86 AVX vzeroupper instructions 17 #include "X86.h" 30 #define DEBUG_TYPE "x86-vzeroupper" 41 const char *getPassName() const override {return "X86 vzeroupper inserter";} 105 return (Reg >= X86::YMM0 && Reg <= X86::YMM15); 118 for (unsigned reg = X86::YMM0; reg <= X86::YMM15; ++reg) { 148 for (unsigned reg = X86::YMM0; reg <= X86::YMM15; ++reg) [all...] |
X86AsmPrinter.cpp | 1 //===-- X86AsmPrinter.cpp - Convert X86 LLVM code to AT&T assembly --------===// 11 // of machine-dependent LLVM code to X86 machine code. 235 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 236 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); 237 const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); 242 BaseReg.getReg() == X86::RIP) 266 assert(IndexReg.getReg() != X86::ESP && 267 "X86 doesn't allow scaling by ESP"); 271 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier); 275 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier) [all...] |
X86ISelLowering.cpp | 1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 10 // This file defines the interfaces that X86 uses to lower LLVM code into a 57 #define DEBUG_TYPE "x86-isel" 62 "x86-experimental-vector-widening-legalization", cl::init(false), 68 "x86-experimental-vector-shuffle-lowering", cl::init(false), 243 // X86 is weird, it always uses i8 for shift amounts and setcc results. 245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 303 addRegisterClass(MVT::i8, &X86::GR8RegClass); 304 addRegisterClass(MVT::i16, &X86::GR16RegClass); 305 addRegisterClass(MVT::i32, &X86::GR32RegClass) [all...] |
X86JITInfo.cpp | 1 //===-- X86JITInfo.cpp - Implement the JIT interfaces for the X86 target --===// 10 // This file implements the JIT interfaces for the X86 target. 43 // X86 doesn't need to invalidate the processor cache, so just invalidate 88 // No need to save EAX/EDX for X86-64. 333 llvm_unreachable("Cannot call X86CompilationCallback() on a non-x86 arch!"); 384 "X86-64 doesn't support rewriting non-stub lazy compilation calls:" 553 switch ((X86::RelocationType)MR->getRelocationType()) { 554 case X86::reloc_pcrel_word: { 561 case X86::reloc_picrel_word: { 568 case X86::reloc_absolute_word [all...] |
X86PadShortFunction.cpp | 18 #include "X86.h" 33 #define DEBUG_TYPE "x86-pad-short-functions" 59 return "X86 Atom pad short functions"; 214 BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP)); 215 BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP));
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X86Subtarget.cpp | 1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===// 10 // This file implements the X86 specific subclass of TargetSubtargetInfo. 39 // Temporary option to control early if-conversion for x86 while adding machine 42 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, 43 cl::desc("Enable early if-conversion on X86")); 77 // X86-64 in PIC mode. 85 // target is x86-64 or the symbol is definitely defined in the current 230 ToggleFeature(X86::Mode64Bit); 232 ToggleFeature(X86::Mode32Bit); 234 ToggleFeature(X86::Mode16Bit) [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
X86MCCodeEmitter.cpp | 1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 45 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 49 return (STI.getFeatureBits() & X86::Mode32Bit) != 0; 53 return (STI.getFeatureBits() & X86::Mode16Bit) != 0; 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 79 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the rang [all...] |
X86ELFObjectWriter.cpp | 1 //===-- X86ELFObjectWriter.cpp - X86 ELF Writer ---------------------------===// 62 case X86::reloc_signed_4byte: 63 case X86::reloc_riprel_4byte_movq_load: 64 case X86::reloc_riprel_4byte: 101 case X86::reloc_global_offset_table8: 104 case X86::reloc_global_offset_table: 128 case X86::reloc_signed_4byte: 162 case X86::reloc_global_offset_table: 188 case X86::reloc_signed_4byte: 207 case X86::reloc_global_offset_table [all...] |
X86MCTargetDesc.cpp | 1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 10 // This file provides X86 specific target descriptions. 214 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 248 ? X86::RIP // Should have dwarf #16. 249 : X86::EIP; // Should have dwarf #8. 287 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 293 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP [all...] |
/external/valgrind/main/VEX/auxprogs/ |
genoffsets.c | 85 // x86 86 GENOFFSET(X86,x86,EAX); 87 GENOFFSET(X86,x86,EBX); 88 GENOFFSET(X86,x86,ECX); 89 GENOFFSET(X86,x86,EDX); 90 GENOFFSET(X86,x86,ESI) [all...] |
/external/chromium_org/third_party/WebKit/Source/platform/audio/ |
DenormalDisabler.h | 34 // Deal with denormals. They can very seriously impact performance on x86. 43 #if COMPILER(GCC) && (CPU(X86) || CPU(X86_64)) 44 // X86 chips can flush denormals 74 #if COMPILER(GCC) && (CPU(X86) || CPU(X86_64))
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VectorMath.cpp | 38 #if CPU(X86) || CPU(X86_64) 60 #if CPU(X86) 69 #if CPU(X86) 78 #if CPU(X86) 96 #if CPU(X86) 128 #if CPU(X86) || CPU(X86_64) 201 #if CPU(X86) || CPU(X86_64) 272 #if CPU(X86) || CPU(X86_64) 281 #if CPU(X86) || CPU(X86_64) 384 #if CPU(X86) || CPU(X86_64 [all...] |
DirectConvolver.cpp | 42 #if (CPU(X86) || CPU(X86_64)) && !(OS(MACOSX) || USE(WEBAUDIO_IPP)) 98 #if CPU(X86) 102 #endif // CPU(X86) 105 #if CPU(X86) || CPU(X86_64) 415 #if CPU(X86) || CPU(X86_64)
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/external/libvpx/ |
config.x86.mk | 6 libvpx_target := x86 16 # X86 asm files are processed by the system and sent to yasm
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/external/llvm/device/include/llvm/Config/ |
Targets.def | 31 LLVM_TARGET(X86)
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/external/llvm/lib/Target/X86/InstPrinter/ |
X86ATTInstPrinter.cpp | 168 // Print X86 immediates as signed values. 186 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 187 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); 188 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); 189 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); 195 printOperand(MI, Op+X86::AddrSegmentReg, O); 211 printOperand(MI, Op+X86::AddrBaseReg, O); 215 printOperand(MI, Op+X86::AddrIndexReg, O); 216 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
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X86IntelInstPrinter.cpp | 166 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 167 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); 168 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); 169 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); 170 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); 174 printOperand(MI, Op+X86::AddrSegmentReg, O); 182 printOperand(MI, Op+X86::AddrBaseReg, O); 190 printOperand(MI, Op+X86::AddrIndexReg, O);
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/ndk/tests/abcc/jni/ |
Abcc.h | 51 X86, 67 if (mAbi == X86) return "x86"; 76 if (mAbi == X86) return "x86"; 100 {"x86", "i686-linux-android", "elf_i386", "-disable-fp-elim -force-align-stack -mattr=-ssse3,-sse41,-sse42,-sse4a,-popcnt -x86-force-gv-stack-cookie", "-dynamic-linker /system/bin/linker"}, 103 {"x86_64", "x86_64-linux-android", "elf_x86_64", "-disable-fp-elim -force-align-stack -mattr=+sse3 -x86-force-gv-stack-cookie", "-dynamic-linker /system/bin/linker64"},
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/external/llvm/include/llvm/Config/ |
llvm-platform-config.h | 15 #define LLVM_NATIVE_ARCH X86
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/external/valgrind/main/coregrind/ |
pub_core_basics.h | 92 ULong r_pc; /* x86:EIP, amd64:RIP, ppc:CIA, arm:R15, mips:pc */ 93 ULong r_sp; /* x86:ESP, amd64:RSP, ppc:R1, arm:R13, mips:sp */ 97 } X86;
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/external/chromium_org/third_party/WebKit/Source/wtf/text/ |
ASCIIFastPath.h | 31 #if OS(MACOSX) && (CPU(X86) || CPU(X86_64)) 107 #if OS(MACOSX) && (CPU(X86) || CPU(X86_64))
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