| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 766 const TargetRegisterClass *RC = MRI->getRegClass(R);
[all...] |
| HexagonVLIWPacketizer.cpp | 557 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 699 MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
700 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
773 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 60 /// getRegClass - Givem a machine instruction descriptor, returns the register
62 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 291 TII->getRegClass(MCID1, 0, TRI, MF));
|
| ARMBaseRegisterInfo.cpp | 596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
|
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 216 return MRI->getRegClass(Reg) == RC;
|
| AMDGPUISelDAGToDAG.cpp | 136 return TM.getRegisterInfo()->getRegClass(RegClass);
140 const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(RCID);
|
| SIISelLowering.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 612 CodeGenRegisterClass *getRegClass(Record*);
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 388 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
472 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
[all...] |
| MachineVerifier.cpp | [all...] |
| EarlyIfConversion.cpp | 484 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
|
| PHIElimination.cpp | 260 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
|
| MachineFunction.cpp | 440 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
[all...] |
| PrologEpilogInserter.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 447 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
448 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 311 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
376 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
692 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | 665 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
895 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 273 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
284 &MRI.getRegClass(ARM::GPRPairRegClassID)));
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 86 return *(RegInfo->getRegClass(RC).begin() + RegNo);
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 394 return *(RegInfo->getRegClass(RC).begin() + RegNo);
[all...] |
