| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/dexbacked/instruction/ |
| DexBackedInstruction30t.java | 32 package org.jf.dexlib2.dexbacked.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction30t;
|
| DexBackedInstruction31i.java | 32 package org.jf.dexlib2.dexbacked.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction31i;
|
| DexBackedInstruction31t.java | 32 package org.jf.dexlib2.dexbacked.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction31t;
|
| DexBackedInstruction32x.java | 32 package org.jf.dexlib2.dexbacked.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction32x;
|
| DexBackedInstruction3rmi.java | 32 package org.jf.dexlib2.dexbacked.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction3rmi;
|
| DexBackedInstruction3rms.java | 32 package org.jf.dexlib2.dexbacked.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction3rms;
|
| DexBackedInstruction51l.java | 32 package org.jf.dexlib2.dexbacked.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction51l;
|
| DexBackedUnknownInstruction.java | 32 package org.jf.dexlib2.dexbacked.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.UnknownInstruction;
|
| /art/compiler/sea_ir/types/ |
| type_inference_visitor.cc | 38 void TypeInferenceVisitor::Visit(UnnamedConstInstructionNode* instruction) {
42 void TypeInferenceVisitor::Visit(PhiInstructionNode* instruction) {
43 std::vector<const Type*> types_to_merge = GetOperandTypes(instruction);
48 void TypeInferenceVisitor::Visit(AddIntInstructionNode* instruction) {
49 std::vector<const Type*> operand_types = GetOperandTypes(instruction);
59 void TypeInferenceVisitor::Visit(MoveResultInstructionNode* instruction) {
60 std::vector<const Type*> operand_types = GetOperandTypes(instruction);
65 void TypeInferenceVisitor::Visit(InvokeStaticInstructionNode* instruction) {
66 FunctionTypeInfo fti(graph_, instruction, type_cache_);
72 InstructionNode* instruction) const
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| InlineMethodResolver.java | 36 import org.jf.dexlib2.iface.instruction.InlineIndexInstruction;
37 import org.jf.dexlib2.iface.instruction.VariableRegisterInstruction;
73 @Nonnull public abstract Method resolveExecuteInline(@Nonnull AnalyzedInstruction instruction);
101 InlineIndexInstruction instruction = (InlineIndexInstruction)analyzedInstruction.instruction; local
102 int inlineIndex = instruction.getInlineIndex();
171 InlineIndexInstruction instruction = (InlineIndexInstruction)analyzedInstruction.instruction; local
172 int inlineIndex = instruction.getInlineIndex();
179 int parameterCount = ((VariableRegisterInstruction)instruction).getRegisterCount()
[all...] |
| /art/disassembler/ |
| disassembler_mips.cc | 34 bool Matches(uint32_t instruction) const {
35 return (instruction & mask) == value;
172 uint32_t instruction = ReadU32(instr_ptr); local
174 uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type.
175 uint32_t rt = (instruction >> 16) & 0x1f; // I-type, R-type.
176 uint32_t rd = (instruction >> 11) & 0x1f; // R-type.
177 uint32_t sa = (instruction >> 6) & 0x1f; // R-type.
183 uint32_t op = (instruction >> 26) & 0x3f;
184 uint32_t function = (instruction & 0x3f); // R-type.
188 if (gMipsInstructions[i].Matches(instruction)) {
[all...] |
| /external/valgrind/main/none/tests/mips64/ |
| branch_and_jump_instructions.c | 107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \
115 instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
118 "end"instruction#RDval":" "\n\t" \
126 printf(instruction" :: out: 0x%llx, RSval: 0x%llx, RTval: 0x%llx\n", \
130 #define TEST4(instruction, RDval, RSval, RD, RS) \
137 instruction" $"#RS", end"instruction#RDval "\n\t" \
140 "end"instruction#RDval":" "\n\t" \
148 printf(instruction" :: out: 0x%llx, RSval: 0x%llx\n",
[all...] |
| /external/lldb/source/Plugins/Instruction/ARM/ |
| EmulationStateARM.h | 54 ReadPseudoMemory (lldb_private::EmulateInstruction *instruction,
62 WritePseudoMemory (lldb_private::EmulateInstruction *instruction,
70 ReadPseudoRegister (lldb_private::EmulateInstruction *instruction,
76 WritePseudoRegister (lldb_private::EmulateInstruction *instruction,
|
| /external/llvm/test/MC/ARM/ |
| invalid-idiv.s | 12 @ ARM-A15: error: instruction requires: divide in ARM
14 @ ARM-A15: error: instruction requires: divide in ARM
16 @ THUMB-A15: error: instruction requires: arm-mode
18 @ THUMB-A15: error: instruction requires: arm-mode
21 @ ARM: error: instruction requires: divide in ARM
23 @ ARM: error: instruction requires: divide in ARM
25 @ THUMB: error: instruction requires: divide in THUMB
27 @ THUMB: error: instruction requires: divide in THUMB
|
| /external/llvm/test/MC/AsmParser/ |
| purgem.s | 12 # CHECK: error: invalid instruction mnemonic 'foo'
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips32.s | 9 sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips32.s | 9 sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips64.s | 8 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| invalid-mips64r2.s | 8 dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips5.s | 8 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips32.s | 9 sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 8 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips32.s | 9 sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/proguard/src/proguard/optimize/peephole/ |
| UnreachableCodeRemover.java | 27 import proguard.classfile.instruction.Instruction;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
123 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
127 System.out.println(" "+(reachableCodeMarker.isReachable(offset) ? "+" : "-")+" "+instruction.toString(offset));
130 // Is this instruction unreachable?
136 // Visit the instruction, if required.
139 instruction.accept(clazz, method, codeAttribute, offset, extraInstructionVisitor);
|
| /art/compiler/sea_ir/code_gen/ |
| code_gen.cc | 118 void CodeGenVisitor::Visit(InstructionNode* instruction) {
119 std::string instr = instruction->GetInstruction()->DumpString(NULL);
123 void CodeGenVisitor::Visit(UnnamedConstInstructionNode* instruction) {
124 std::string instr = instruction->GetInstruction()->DumpString(NULL);
125 std::cout << "1.Instruction: " << instr << std::endl;
126 llvm_data_->AddValue(instruction,
127 llvm::ConstantInt::get(*llvm_data_->context_, llvm::APInt(32, instruction->GetConstValue())));
130 void CodeGenVisitor::Visit(ConstInstructionNode* instruction) {
131 std::string instr = instruction->GetInstruction()->DumpString(NULL);
132 std::cout << "1.Instruction: " << instr << std::endl
[all...] |
