| /external/tremolo/Tremolo/ |
| mdctLARM.s | 816 SUB r11,r10,r11,LSL #1 @ r11= s5 = x[4] - x[5]
820 ADD r2, r11,r9 @ r2 = x[0] = s5 + s3
821 SUB r4, r2, r9, LSL #1 @ r4 = x[2] = s5 - s3
845 SUB r11,r10,r11,LSL #1 @ r11= s5 = x[4] - x[5]
849 ADD r2, r11,r9 @ r2 = x[0] = s5 + s3
850 SUB r4, r2, r9, LSL #1 @ r4 = x[2] = s5 - s3
932 SUB r11,r10,r11,LSL #1 @ r11= s5 = x[4] - x[5]
936 ADD r2, r11,r9 @ r2 = x[0] = s5 + s3
937 SUB r4, r2, r9, LSL #1 @ r4 = x[2] = s5 - s3
961 SUB r11,r10,r11,LSL #1 @ r11= s5 = x[4] - x[5
[all...] |
| /external/chromium_org/third_party/WebKit/Source/wtf/ |
| dtoa.cpp | 743 j, j1, k, k0, k_check, m2, m5, s2, s5, local
836 s5 = k;
841 s5 = 0;
1027 if (s5 > 0)
1028 pow5mult(S, s5);
1047 if ((i = ((s5 ? 32 - hi0bits(S.words()[S.size() - 1]) : 1) + s2) & 0x1f))
[all...] |
| /art/test/004-JniTest/ |
| jni_test.cc | 201 jshort s3, jshort s4, jshort s5, jshort s6,
207 assert(s5 == -5);
|
| /art/test/115-native-bridge/ |
| nativebridge.cc | 143 jshort s3, jshort s4, jshort s5, jshort s6,
149 return fnPtr(env, klass, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10);
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/armv7/ |
| armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S | 70 #define x2i s5
76 #define t1i s5
|
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 84 #define w0i s5
|
| omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 94 #define x1i s5
|
| /external/clang/test/CodeGen/ |
| arm64-arguments.c | 27 struct s5 { struct { } f0; int f1; }; struct
28 struct s5 f5(void) {}
|
| /external/clang/test/OpenMP/ |
| for_reduction_messages.cpp | 47 class S5 {
49 S5() : a(0) {}
50 S5(const S5 &s5) : a(s5.a) {}
51 S5 &operator+=(const S5 &arg);
54 S5(int v) : a(v) {}
212 S5 g(5); // expected-note {{'g' defined here}
[all...] |
| parallel_for_reduction_messages.cpp | 47 class S5 {
49 S5() : a(0) {}
50 S5(const S5 &s5) : a(s5.a) {}
51 S5 &operator+=(const S5 &arg);
54 S5(int v) : a(v) {}
185 S5 g(5); // expected-note {{'g' defined here}
[all...] |
| simd_reduction_messages.cpp | 47 class S5 {
49 S5() : a(0) {}
50 S5(const S5 &s5) : a(s5.a) {}
51 S5 &operator+=(const S5 &arg);
54 S5(int v) : a(v) {}
188 S5 g(5); // expected-note {{'g' defined here}
[all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5.s | 11 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 13 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 17 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips3.s | 24 teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/openssl/crypto/bn/asm/ |
| alpha-mont.pl | 41 $m1="s5";
64 stq s5,24(sp)
312 ldq s5,24(sp)
|
| mips3-mont.pl | 42 $i="s5";
90 sd s5,40($fp)
315 ld s5,40($fp)
|
| /external/openssl/crypto/sha/asm/ |
| sha1-alpha.pl | 250 stq s5,48(sp)
312 ldq s5,48(sp)
|
| /external/chromium_org/third_party/libvpx/source/libvpx/vp9/common/arm/neon/ |
| vp9_iht4x4_add_neon.asm | 66 vmull.s16 q8, d4, d19 ; s5 = sinpi_2_9 * x3
70 vadd.s32 q10, q10, q13 ; x0 = s0 + s3 + s5
|
| /external/libvpx/libvpx/vp9/common/arm/neon/ |
| vp9_iht4x4_add_neon.asm | 66 vmull.s16 q8, d4, d19 ; s5 = sinpi_2_9 * x3
70 vadd.s32 q10, q10, q13 ; x0 = s0 + s3 + s5
|
| /external/llvm/test/MC/ARM/ |
| single-precision-fp.s | 80 vcvt.s32.f64 s5, d4
97 @ CHECK-ERRORS-NEXT: vcvt.s32.f64 s5, d4
|
| /external/llvm/test/MC/Mips/ |
| mips-register-names-o32.s | 29 addiu $s5, $zero, 0 # CHECK: encoding: [0x24,0x15,0x00,0x00]
|
| mips64-register-names-n32-n64.s | 35 daddiu $s5, $zero, 0 # CHECK: encoding: [0x64,0x15,0x00,0x00]
|
| mips64-register-names-o32.s | 30 daddiu $s5, $zero, 0 # CHECK: encoding: [0x64,0x15,0x00,0x00]
|
| set-at-directive.s | 110 .set at=$s5
|
