/external/clang/test/CodeGen/ |
bitfield-2.c | 272 // CHECK-RECORD: Record: RecordDecl{{.*}}s7 274 // CHECK-RECORD: LLVMType:%struct.s7 = type { i32, i32, i32, i8, i32, [12 x i8] } 280 struct __attribute__((aligned(16))) s7 { struct 286 int f7_load(struct s7 *a0) {
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arm64-arguments.c | 35 struct s7 { struct { int : 0; } f0; }; struct 36 struct s7 f7(void) {} 67 void f15(struct s7 a0) {}
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/external/llvm/test/MC/Mips/mips5/ |
invalid-mips64.s | 21 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/valgrind/main/none/tests/arm/ |
vfp.stdout.exp | 143 vmla.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 154 vmla.f32 s29, s15, s7 :: Sd 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 160 vmla.f32 s29, s25, s7 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 192 vnmla.f32 s7, s1, s6 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 203 vnmla.f32 s29, s15, s7 :: Sd 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 209 vnmla.f32 s29, s25, s7 :: Sd 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 241 vmls.f32 s7, s1, s6 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 252 vmls.f32 s29, s15, s7 :: Sd 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 258 vmls.f32 s29, s25, s7 :: Sd 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 290 vnmls.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc0000 [all...] |
vfpv4_fma.stdout.exp | 27 vfma.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 38 vfma.f32 s29, s15, s7 :: Qd 0x55555555 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 44 vfma.f32 s29, s25, s7 :: Qd 0x55555555 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 76 vfms.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 87 vfms.f32 s29, s15, s7 :: Qd 0x55555555 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 93 vfms.f32 s29, s25, s7 :: Qd 0x55555555 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
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/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/armv7/ |
armSP_FFT_CToC_FC32_Radix4_fs_unsafe_s.S | 72 #define x3i s7
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omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 83 #define w0i s7
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/external/chromium_org/v8/test/cctest/ |
test-disasm-mips.cc | 496 COMPARE(clz(s6, s7), 497 "02e0b050 clz s6, s7"); 503 COMPARE(clz(s6, s7), 504 "72f6b020 clz s6, s7"); 513 COMPARE(ins_(s6, s7, 30, 2), 514 "7ef6ff84 ins s6, s7, 30, 2"); 519 COMPARE(ext_(s6, s7, 30, 2), 520 "7ef60f80 ext s6, s7, 30, 2");
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test-disasm-mips64.cc | 647 COMPARE(clz(s6, s7), 648 "02e0b050 clz s6, s7"); 654 COMPARE(clz(s6, s7), 655 "72f6b020 clz s6, s7"); 662 COMPARE(ins_(s6, s7, 30, 2), 663 "7ef6ff84 ins s6, s7, 30, 2"); 668 COMPARE(ext_(s6, s7, 30, 2), 669 "7ef60f80 ext s6, s7, 30, 2");
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/external/llvm/test/MC/Mips/mips2/ |
invalid-mips32.s | 30 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 39 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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invalid-mips32r2.s | 18 ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 37 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 46 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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invalid-mips4.s | 24 dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 49 ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 59 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips64r6/ |
invalid-mips64.s | 16 dmult $s7,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 31 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/openssl/crypto/bn/asm/ |
mips-mont.pl | 30 ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23)); 46 # ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23)); 108 $nhi=$s7; 153 $REG_S $s7,($FRAMESIZE-6)*$SZREG($sp) 405 $REG_L $s7,($FRAMESIZE-6)*$SZREG($sp)
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/bionic/libc/arch-mips/bionic/ |
setjmp.S | 79 REG_S s7, SC_REGS+S7*REGSZ(a0) 144 REG_L s7, SC_REGS+S7*REGSZ(a0)
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/bionic/libc/arch-mips64/bionic/ |
setjmp.S | 79 REG_S s7, SC_REGS+S7*REGSZ(a0) 144 REG_L s7, SC_REGS+S7*REGSZ(a0)
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/development/ndk/sources/android/libportable/arch-mips/ |
setjmp.S | 92 REG_S s7, JB_S7(a0) 174 REG_L s7, JB_S7(a0)
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/external/llvm/test/MC/Mips/mips4/ |
invalid-mips64.s | 20 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/art/runtime/arch/mips/ |
quick_entrypoints_mips.S | 49 sw $s7, 48($sp) 89 sw $s7, 48($sp) 111 lw $s7, 48($sp) 134 lw $s7, 48($sp) 171 sw $s7, 48($sp) 199 lw $s7, 48($sp) 326 lw $s7, 92($a0) [all...] |
/external/valgrind/main/none/tests/mips32/ |
branches.c | 268 TESTINST1(21, s7); 294 TESTINST2(21, s7); 320 TESTINST3(21, s7); 670 TESTINST3j(21, s7); 696 TESTINST3ja(21, s7);
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/external/llvm/test/MC/ARM/ |
simple-fp-encoding.s | 15 vdiv.f32 s5, s7 20 @ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee] 289 @ CHECK: vldmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x91,0xec] 291 vldmia r1, {s2,s3-s6,s7} 294 @ CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x81,0xec] 297 vstmia r1, {s2,s3-s6,s7}
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/external/openssl/crypto/sha/asm/ |
sha1-mips.pl | 26 ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23)); 42 # ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23)); 262 $REG_S $s7,($FRAMESIZE-7)*$SZREG($sp) 334 $REG_L $s7,($FRAMESIZE-7)*$SZREG($sp)
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sha512-mips.pl | 28 ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23)); 45 # ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23)); 270 $REG_S $s7,$FRAMESIZE-7*$SZREG($sp) 363 $REG_L $s7,$FRAMESIZE-7*$SZREG($sp)
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/external/tremolo/Tremolo/ |
mdct.c | 113 REG_TYPE s7 = x[6] - x[7]; local 116 x[1] = s7 - s1; 118 x[3] = s7 + s1;
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mdctLARM.s | 818 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7] 822 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1 823 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1 847 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7] 851 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1 852 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1 934 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7] 938 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1 939 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1 963 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7 [all...] |