| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-19/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-21/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/machine/ |
| regdef.h | 68 #define t6 $14 macro
|
| /external/pixman/pixman/ |
| pixman-mips-memcpy-asm.S | 113 lw t6, 24(a1)
123 sw t6, 24(a0)
135 lw t6, 56(a1)
145 sw t6, 56(a0)
169 lw t6, 24(a1)
179 sw t6, 24(a0)
266 LWHI t6, 24(a1)
267 LWLO t6, 27(a1)
278 sw t6, 24(a0)
296 LWHI t6, 56(a1
[all...] |
| pixman-mips-dspr2-asm.S | 154 li t6, 0x001f001f
161 CONVERT_2x8888_TO_2x0565 t0, t1, t2, t3, t4, t5, t6, t7, t8
203 CONVERT_2x0565_TO_2x8888 t0, t1, t2, t3, t4, t5, t6, t7, t8, t9
249 lw t6, 24(a1)
258 or t6, t6, t9
267 sw t6, 24(a0)
278 lw t6, 24(a1)
287 or t6, t6, t
[all...] |
| /external/clang/test/CodeGen/ |
| ms_struct-bitfield.c | 73 } ATTR t6; variable in typeref:struct:__anon23302
74 int s6 = sizeof(t6);
|
| arm-aapcs-zerolength-bitfield.c | 52 struct t6 struct
59 static int arr6_offset[(offsetof(struct t6, bar2) == 2) ? 0 : -1];
60 static int arr6_sizeof[(sizeof(struct t6) == 4) ? 0 : -1];
|
| arm-apcs-zerolength-bitfield.c | 56 struct t6 struct
63 static int arr6_offset[(offsetof(struct t6, bar2) == 5) ? 0 : -1];
64 static int arr6_sizeof[(sizeof(struct t6) == 8) ? 0 : -1];
|
| /external/clang/test/CodeGenCXX/ |
| rtti-linkage.cpp | 167 inline void t6() { function
172 t6();
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| invalid-mips64r2.s | 8 dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/compiler-rt/test/asan/TestCases/ |
| stack-overflow.cc | 36 int t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13;
43 t6 = z6;
58 z6 = t6;
|
| /external/valgrind/main/memcheck/tests/ |
| origin3-no.stderr.exp | 52 at 0x........: t6 (origin3-no.c:107)
55 at 0x........: t6 (origin3-no.c:104)
61 at 0x........: t6 (origin3-no.c:109)
64 at 0x........: t6 (origin3-no.c:105)
70 at 0x........: t6 (origin3-no.c:111)
73 at 0x........: t6 (origin3-no.c:105)
|
| /bionic/libc/arch-mips64/include/machine/ |
| regdef.h | 75 #define t6 $14 macro
|
| /development/ndk/platforms/android-L/arch-mips64/include/machine/ |
| regdef.h | 75 #define t6 $14 macro
|
| /external/clang/test/Analysis/ |
| free.c | 29 void t6 () { function
|
| /external/clang/test/Parser/ |
| ms-inline-asm.c | 17 int t6() {
|
| /external/clang/test/Sema/ |
| attr-cleanup.c | 46 void t6(void) { function
|
