| /external/mesa3d/src/gallium/drivers/nv30/ |
| nv30_state.c | 221 SB_DATA (so, cso->depth.writemask);
227 SB_DATA (so, cso->stencil[0].writemask);
243 SB_DATA (so, cso->stencil[1].writemask);
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| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_vec4.h | 136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
142 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:brw::dst_reg
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| brw_eu_emit.c | 128 insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask;
785 insn->bits1.da3src.dest_writemask = dest.dw1.bits.writemask;
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4.h | 136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
142 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:brw::dst_reg
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| brw_eu_emit.c | 128 insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask;
785 insn->bits1.da3src.dest_writemask = dest.dw1.bits.writemask;
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_aos.c | 323 * Writemask
326 if (reg->Register.WriteMask != TGSI_WRITEMASK_XYZW) {
327 LLVMValueRef writemask; local
329 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
331 reg->Register.WriteMask,
335 mask = LLVMBuildAnd(builder, mask, writemask, "");
337 mask = writemask;
471 * assume a full writemask and then let LLVM optimization passes eliminate
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/softpipe/ |
| sp_quad_depth_test.c | 420 * \param wrtMask writemask controlling which bits are changed in the
504 /* apply bit-wise stencil buffer writemask */
586 /* Update our internal copy only if writemask set. Even if
587 * depth.writemask is FALSE, may still need to write out buffer
590 if (softpipe->depth_stencil->depth.writemask) {
632 wrtMask = softpipe->depth_stencil->stencil[face].writemask;
813 if (qs->softpipe->depth_stencil->depth.writemask)
894 boolean depthwrite = qs->softpipe->depth_stencil->depth.writemask;
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/svga/ |
| svga_context.h | 93 uint8_t writemask; member in struct:svga_blend_state::__anon18741
124 /* SVGA3D has one ref/mask/writemask triple shared between front &
|
| svga_pipe_blend.c | 198 blend->rt[i].writemask = templ->rt[0].colormask;
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| svga_state_rss.c | 91 EMIT_RS( svga, curr->rt[0].writemask, COLORWRITEENABLE, fail );
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_aos.c | 323 * Writemask
326 if (reg->Register.WriteMask != TGSI_WRITEMASK_XYZW) {
327 LLVMValueRef writemask; local
329 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
331 reg->Register.WriteMask,
335 mask = LLVMBuildAnd(builder, mask, writemask, "");
337 mask = writemask;
471 * assume a full writemask and then let LLVM optimization passes eliminate
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| /external/mesa3d/src/gallium/drivers/softpipe/ |
| sp_quad_depth_test.c | 420 * \param wrtMask writemask controlling which bits are changed in the
504 /* apply bit-wise stencil buffer writemask */
586 /* Update our internal copy only if writemask set. Even if
587 * depth.writemask is FALSE, may still need to write out buffer
590 if (softpipe->depth_stencil->depth.writemask) {
632 wrtMask = softpipe->depth_stencil->stencil[face].writemask;
813 if (qs->softpipe->depth_stencil->depth.writemask)
894 boolean depthwrite = qs->softpipe->depth_stencil->depth.writemask;
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| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_context.h | 93 uint8_t writemask; member in struct:svga_blend_state::__anon32138
124 /* SVGA3D has one ref/mask/writemask triple shared between front &
|
| svga_pipe_blend.c | 198 blend->rt[i].writemask = templ->rt[0].colormask;
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/ |
| i915_fpc_translate.c | 322 * Compute flags for saturation and writemask.
327 const uint writeMask
328 = inst->Dst[0].Register.WriteMask;
334 if (writeMask & TGSI_WRITEMASK_X)
336 if (writeMask & TGSI_WRITEMASK_Y)
338 if (writeMask & TGSI_WRITEMASK_Z)
340 if (writeMask & TGSI_WRITEMASK_W)
497 uint writemask; local
672 A0_DEST_CHANNEL_ALL, /* dest writemask */
687 A0_DEST_CHANNEL_ALL, /* dest writemask */
[all...] |
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_translate.c | 322 * Compute flags for saturation and writemask.
327 const uint writeMask
328 = inst->Dst[0].Register.WriteMask;
334 if (writeMask & TGSI_WRITEMASK_X)
336 if (writeMask & TGSI_WRITEMASK_Y)
338 if (writeMask & TGSI_WRITEMASK_Z)
340 if (writeMask & TGSI_WRITEMASK_W)
497 uint writemask; local
672 A0_DEST_CHANNEL_ALL, /* dest writemask */
687 A0_DEST_CHANNEL_ALL, /* dest writemask */
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/llvmpipe/ |
| lp_state_fs.c | 276 if (!(key->depth.enabled && key->depth.writemask) &&
277 !(key->stencil[0].enabled && key->stencil[0].writemask))
505 if (!(key->depth.enabled && key->depth.writemask) &&
506 !(key->stencil[0].enabled && key->stencil[0].writemask))
[all...] |
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_state_fs.c | 276 if (!(key->depth.enabled && key->depth.writemask) &&
277 !(key->stencil[0].enabled && key->stencil[0].writemask))
505 if (!(key->depth.enabled && key->depth.writemask) &&
506 !(key->stencil[0].enabled && key->stencil[0].writemask))
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_compiler.c | 168 * writemask is honoured.
170 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask)
182 inst->U.I.DstReg.WriteMask &= writemask;
253 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
264 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ;
279 inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ;
333 inst_add->U.I.DstReg.WriteMask = RC_MASK_X;
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/trace/ |
| tr_dump_state.c | 317 trace_dump_member(bool, &state->depth, writemask);
333 trace_dump_member(uint, &state->stencil[i], writemask);
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| /external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/ |
| st_cb_clear.c | 258 depth_stencil.depth.writemask = 1;
271 depth_stencil.stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
364 = (ctx->Stencil.WriteMask[0] & stencilMax) != stencilMax;
417 = (ctx->Stencil.WriteMask[0] & stencilMax) != stencilMax;
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_compiler.c | 168 * writemask is honoured.
170 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask)
182 inst->U.I.DstReg.WriteMask &= writemask;
253 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
264 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ;
279 inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ;
333 inst_add->U.I.DstReg.WriteMask = RC_MASK_X;
|
| /external/mesa3d/src/gallium/drivers/trace/ |
| tr_dump_state.c | 317 trace_dump_member(bool, &state->depth, writemask);
333 trace_dump_member(uint, &state->stencil[i], writemask);
|
| /external/mesa3d/src/mesa/state_tracker/ |
| st_cb_clear.c | 258 depth_stencil.depth.writemask = 1;
271 depth_stencil.stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
364 = (ctx->Stencil.WriteMask[0] & stencilMax) != stencilMax;
417 = (ctx->Stencil.WriteMask[0] & stencilMax) != stencilMax;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/postprocess/ |
| pp_mlaa.c | 106 mstencil.stencil[0].valuemask = mstencil.stencil[0].writemask = ~0;
|
