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  /external/llvm/test/MC/Mips/
mips-register-names-o32.s 4 # Second byte of addiu with $zero at rt contains the number of the source
8 addiu $zero, $zero, 0 # CHECK: encoding: [0x24,0x00,0x00,0x00] label
9 addiu $at, $zero, 0 # CHECK: encoding: [0x24,0x01,0x00,0x00] label
10 addiu $v0, $zero, 0 # CHECK: encoding: [0x24,0x02,0x00,0x00] label
11 addiu $v1, $zero, 0 # CHECK: encoding: [0x24,0x03,0x00,0x00] label
12 addiu $a0, $zero, 0 # CHECK: encoding: [0x24,0x04,0x00,0x00] label
13 addiu $a1, $zero, 0 # CHECK: encoding: [0x24,0x05,0x00,0x00] label
14 addiu $a2, $zero, 0 # CHECK: encoding: [0x24,0x06,0x00,0x00] label
15 addiu $a3, $zero, 0 # CHECK: encoding: [0x24,0x07,0x00,0x00] label
16 addiu $t0, $zero, 0 # CHECK: encoding: [0x24,0x08,0x00,0x00 label
17 addiu $t1, $zero, 0 # CHECK: encoding: [0x24,0x09,0x00,0x00] label
18 addiu $t2, $zero, 0 # CHECK: encoding: [0x24,0x0a,0x00,0x00] label
19 addiu $t3, $zero, 0 # CHECK: encoding: [0x24,0x0b,0x00,0x00] label
20 addiu $t4, $zero, 0 # CHECK: encoding: [0x24,0x0c,0x00,0x00] label
21 addiu $t5, $zero, 0 # CHECK: encoding: [0x24,0x0d,0x00,0x00] label
22 addiu $t6, $zero, 0 # CHECK: encoding: [0x24,0x0e,0x00,0x00] label
23 addiu $t7, $zero, 0 # CHECK: encoding: [0x24,0x0f,0x00,0x00] label
24 addiu $s0, $zero, 0 # CHECK: encoding: [0x24,0x10,0x00,0x00] label
25 addiu $s1, $zero, 0 # CHECK: encoding: [0x24,0x11,0x00,0x00] label
26 addiu $s2, $zero, 0 # CHECK: encoding: [0x24,0x12,0x00,0x00] label
27 addiu $s3, $zero, 0 # CHECK: encoding: [0x24,0x13,0x00,0x00] label
28 addiu $s4, $zero, 0 # CHECK: encoding: [0x24,0x14,0x00,0x00] label
29 addiu $s5, $zero, 0 # CHECK: encoding: [0x24,0x15,0x00,0x00] label
30 addiu $s6, $zero, 0 # CHECK: encoding: [0x24,0x16,0x00,0x00] label
31 addiu $s7, $zero, 0 # CHECK: encoding: [0x24,0x17,0x00,0x00] label
32 addiu $t8, $zero, 0 # CHECK: encoding: [0x24,0x18,0x00,0x00] label
33 addiu $t9, $zero, 0 # CHECK: encoding: [0x24,0x19,0x00,0x00] label
34 addiu $k0, $zero, 0 # CHECK: encoding: [0x24,0x1a,0x00,0x00] label
35 addiu $k1, $zero, 0 # CHECK: encoding: [0x24,0x1b,0x00,0x00] label
36 addiu $gp, $zero, 0 # CHECK: encoding: [0x24,0x1c,0x00,0x00] label
37 addiu $sp, $zero, 0 # CHECK: encoding: [0x24,0x1d,0x00,0x00] label
38 addiu $fp, $zero, 0 # CHECK: encoding: [0x24,0x1e,0x00,0x00] label
39 addiu $s8, $zero, 0 # CHECK: encoding: [0x24,0x1e,0x00,0x00] label
40 addiu $ra, $zero, 0 # CHECK: encoding: [0x24,0x1f,0x00,0x00] label
    [all...]
do_switch2.s 26 addiu $2, $2, %lo(_gp_disp)
27 addiu $sp, $sp, -8
28 addiu $1, $zero, 2
35 addiu $2, $zero, 4
37 addiu $sp, $sp, 8
47 addiu $2, $zero, 1
49 addiu $sp, $sp, 8
51 addiu $2, $zero, 2
53 addiu $sp, $sp, 8
55 addiu $2, $zero,
    [all...]
do_switch1.s 26 addiu $sp, $sp, -8
27 addiu $1, $zero, 2
34 addiu $2, $zero, 4
36 addiu $sp, $sp, 8
45 addiu $2, $zero, 1
47 addiu $sp, $sp, 8
49 addiu $2, $zero, 2
51 addiu $sp, $sp, 8
53 addiu $2, $zero, 0
55 addiu $sp, $sp,
    [all...]
do_switch3.s 28 addiu $1, $zero, 2
36 addiu $2, $zero, 4
52 addiu $2, $zero, 1
56 addiu $2, $zero, 2
60 addiu $2, $zero, 0
64 addiu $2, $zero, 3
elf-tls.s 32 addiu $2, $2, %lo(_gp_disp)
33 addiu $sp, $sp, -24
38 addiu $4, $gp, %tlsgd(t1)
42 addiu $sp, $sp, 24
64 addiu $2, $2, %lo(_gp_disp)
65 addiu $sp, $sp, -24
70 addiu $4, $gp, %tlsgd(t2)
74 addiu $sp, $sp, 24
96 addiu $2, $2, %lo(_gp_disp)
97 addiu $sp, $sp, -2
    [all...]
micromips-el-fixup-data.s 16 addiu $sp, $sp, -16
24 addiu $sp, $sp, 16
  /external/chromium_org/third_party/webrtc/common_audio/signal_processing/
filter_ar_fast_q12_mips.c 34 "addiu %[i], %[data_length], 0 \n\t"
36 "addiu %[j], %[coefficients_length], -1 \n\t"
40 "addiu %[inptr], %[data_in], 0 \n\t"
45 "addiu %[i], %[i], -1 \n\t"
46 "addiu %[tmpout], %[outptr], 0 \n\t"
53 "addiu %[tmpout], %[tmpout], 4 \n\t"
56 "addiu %[j], %[j], -2 \n\t"
58 " addiu %[coefptr], %[coefptr], -4 \n\t"
65 "addiu %[inptr], %[inptr], 2 \n\t"
66 "addiu %[j], %[coefficients_length], -1 \n\t
    [all...]
  /external/llvm/test/CodeGen/Mips/
inlineasm_constraint.ll 8 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},4096
10 tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind
14 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
16 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind
20 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},0
22 tail call i32 asm sideeffect "addiu $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
38 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
40 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind
44 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
46 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwin
    [all...]
inlineasm-cnstrnt-reg.ll 11 ;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},23
13 tail call i8 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind
17 ;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},13
19 tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind
23 ;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3
25 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind
29 ; CHECK: addiu $25,${{[0-9]+}},1024
31 tail call i32 asm sideeffect "addiu $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
inlineasm-cnstrnt-reg64.ll 15 ;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3
17 tail call i64 asm sideeffect "addiu $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
stack-alignment.ll 5 ; 32: addiu $sp, $sp, -8
6 ; 64: addiu $sp, $sp, -16
addi.ll 23 ; 16: addiu ${{[0-9]+}}, 5 # 16 bit inst
24 ; 16: addiu ${{[0-9]+}}, -5 # 16 bit inst
25 ; 16: addiu ${{[0-9]+}}, 10000
26 ; 16: addiu ${{[0-9]+}}, -10000
stacksize.ll 6 ; CHECK-NOT: addiu $sp, $sp
o32_cc.ll 56 ; CHECK-DAG: addiu $4, $zero, 12
57 ; CHECK-DAG: addiu $5, $zero, 13
58 ; CHECK-DAG: addiu $6, $zero, 14
59 ; CHECK-DAG: addiu $7, $zero, 15
71 ; CHECK-DAG: addiu $6, $zero, 23
85 ; CHECK-DAG: addiu $6, $zero, 33
86 ; CHECK-DAG: addiu $7, $zero, 24
98 ; CHECK-DAG: addiu $5, $zero, 43
99 ; CHECK-DAG: addiu $6, $zero, 34
110 ; CHECK-DAG: addiu $4, $zero, 2
    [all...]
cttz-v.ll 8 ; MIPS32-DAG: addiu $[[R0:[0-9]+]], $4, -1
12 ; MIPS32-DAG: addiu $[[R4:[0-9]+]], $zero, 32
14 ; MIPS32-DAG: addiu $[[R5:[0-9]+]], $5, -1
21 ; MIPS64-DAG: addiu $[[R0:[0-9]+]], $4, -1
25 ; MIPS64-DAG: addiu $[[R4:[0-9]+]], $zero, 32
27 ; MIPS64-DAG: addiu $[[R5:[0-9]+]], $5, -1
eh-dwarf-cfa.ll 16 ; CHECK: addiu $sp, $sp, -32
17 ; CHECK: addiu $2, $sp, 32
29 ; CHECK: addiu $[[R0]], $[[R0]], -8
35 ; CHECK: addiu $2, $[[R1]], 8
49 ; CHECK: addiu $sp, $sp, -40
52 ; CHECK: addiu $[[R0:[a-z0-9]+]], $fp, 40
imm.ll 22 ; CHECK: addiu ${{[0-9]+}}, $zero, 4660
29 ; CHECK: addiu ${{[0-9]+}}, $zero, -32204
  /external/chromium_org/third_party/webrtc/modules/audio_coding/codecs/isac/fix/source/
transform_mips.c 41 "addiu %[inre1], %[inre1Q9], 0 \n\t"
42 "addiu %[inre2], %[inre2Q9], 0 \n\t"
43 "addiu %[tmpre], %[tmpreQ16], 0 \n\t"
44 "addiu %[tmpim], %[tmpimQ16], 0 \n\t"
45 "addiu %[factor], $zero, 16921 \n\t"
67 "addiu %[k], %[k], -2 \n\t"
82 "addiu %[inre1], %[inre1], 4 \n\t"
83 "addiu %[inre2], %[inre2], 4 \n\t"
86 "addiu %[cosptr], %[cosptr], 4 \n\t"
87 "addiu %[sinptr], %[sinptr], 4 \n\t
    [all...]
  /external/pixman/pixman/
pixman-mips-dspr2-asm.S 47 addiu a0, a0, 2
48 addiu a1, a1, -2
55 addiu t1, t1, -1
57 addiu a1, a1, -32
68 addiu a0, a0, 32
78 addiu a0, a0, 32
81 addiu a1, a1, -2
84 addiu a0, a0, 2
104 addiu t1, t1, -1
106 addiu a1, a1, -3
    [all...]
  /external/valgrind/main/none/tests/mips64/
arithmetic_instruction.stdout.exp-mips64     [all...]
arithmetic_instruction.stdout.exp-mips64r2     [all...]
rounding_mode.h 29 "addiu $t0, 1" "\n\t"
41 "addiu $t0, 2" "\n\t"
53 "addiu $t0, 3" "\n\t"
  /external/chromium_org/third_party/webrtc/modules/audio_processing/ns/
nsx_core_mips.c 63 "addiu %[r6], %[r3], -11 \n\t"
83 "addiu %[r1], %[r7], 37 \n\t"
84 "addiu %[r5], %[r5], -31 \n\t"
277 "addiu %[r7], %[r7], -1 \n\t"
282 "addiu %[r3], %[r2], 8 \n\t"
283 "addiu %[r2], %[r2], -4 \n\t"
295 "addiu %[r4], %[r4], -1 \n\t"
299 "addiu %[r6], %[r7], -7 \n\t"
303 "addiu %[r4], %[r6], -8 \n\t"
409 "addiu %[window], %[window], 16 \n\t
    [all...]
  /external/llvm/test/CodeGen/Mips/cconv/
stack-alignment.ll 23 ; O32: addiu $sp, $sp, -8
24 ; O32: addiu $sp, $sp, 8
25 ; N32: addiu $sp, $sp, -16
26 ; N32: addiu $sp, $sp, 16
27 ; N64: addiu $sp, $sp, -16
28 ; N64: addiu $sp, $sp, 16
  /external/llvm/lib/Target/Mips/
MipsAnalyzeImmediate.cpp 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
56 // A single ADDiu will do if RemSize <= 16.
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
71 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi.
79 // Replace a ADDiu & SLL pair with a LUi.
81 // ADDiu 0x0111
86 // Check if the first two instructions are ADDiu and SLL and the shift amount
88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
92 // Sign-extend and shift operand of ADDiu and see if it still fits in 16-bit.
130 ADDiu = Mips::ADDiu
    [all...]

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