| /external/llvm/lib/Target/Sparc/ |
| SparcInstrAliases.td | 68 (BCOND brtarget:$imm, condVal)>;
72 (BCONDA brtarget:$imm, condVal)>;
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>
[all...] |
| SparcInstrInfo.td | 109 def brtarget : Operand<OtherVT> {
585 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
631 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
634 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
671 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
674 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips32r6InstrInfo.td | 323 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
335 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
336 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
337 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
338 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
340 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
341 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
343 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
344 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
346 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>
[all...] |
| Mips64InstrInfo.td | 178 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
179 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
180 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
181 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
182 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
183 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
270 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
|
| MipsInstrInfo.td | 344 def brtarget : Operand<OtherVT> {
728 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
729 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
787 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
788 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
[all...] |
| Mips16InstrInfo.td | 41 FI16<op, (outs), (ins brtarget:$imm16),
99 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
138 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
201 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
265 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
277 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
[all...] |
| MipsInstrFPU.td | 527 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
529 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
594 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
596 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
|
| /external/llvm/lib/Target/X86/ |
| X86InstrTSX.td | 27 def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget:$dst),
|
| X86InstrControl.td | 60 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
62 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
76 def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
79 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIInstructions.td | [all...] |
| AMDILInstrInfo.td | 73 def brtarget : Operand<OtherVT>;
184 (ins brtarget:$target, GPRI32:$src0),
188 (ins brtarget:$target, GPRF32:$src0),
221 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstructions.td | [all...] |
| AMDILInstrInfo.td | 73 def brtarget : Operand<OtherVT>;
184 (ins brtarget:$target, GPRI32:$src0),
188 (ins brtarget:$target, GPRF32:$src0),
221 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.td | 192 def brtarget : Operand<OtherVT>;
286 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
288 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
653 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
655 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstructions.td | 381 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
388 0x00000004, (ins brtarget:$target, SCCReg:$scc),
392 0x00000005, (ins brtarget:$target, SCCReg:$scc),
399 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
404 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
411 0x00000008, (ins brtarget:$target, EXECReg:$exec),
416 0x00000009, (ins brtarget:$target, EXECReg:$exec),
[all...] |
| R600Instructions.td | [all...] |
| AMDGPUInstructions.td | 55 def brtarget : Operand<OtherVT>;
|
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.cpp | 932 TYPE("brtarget", TYPE_RELv)
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 3877 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; local
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | [all...] |
| HexagonOperands.td | 846 def brtarget : Operand<OtherVT>;
|
| HexagonInstrInfo.td | 772 JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
[all...] |
| HexagonInstrInfoV4.td | 19 def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.td | 33 def brtarget : Operand<OtherVT>;
[all...] |
| /external/llvm/docs/ |
| WritingAnLLVMBackend.rst | [all...] |
