| /external/valgrind/main/none/tests/mips64/ |
| move_instructions.stdout.exp-BE | 2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b50
[all...] |
| move_instructions.stdout.exp-LE | 2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b50
[all...] |
| load_store_unaligned.c | 34 "dmfc1 %0, $f0" "\n\t"
|
| macro_load_store.h | 56 "dmfc1 %0, $f0" "\n\t" \
112 "dmfc1 %0, $f0" "\n\t" \
|
| macro_fpu.h | 150 "dmfc1 %1, $f0" "\n\t" \
172 "dmfc1 %1, $f0" "\n\t" \
|
| move_instructions.c | 79 "dmfc1 $t1, $f0" "\n\t" \
87 printf("dmtc1, mov.d, dmfc1 :: mem: 0x%llx out: 0x%llx\n", \
129 "dmfc1 %0, $"#FD "\n\t" \
168 "dmfc1 %0, $"#FD "\n\t" \
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64-libcall.ll | 9 ; HARD-NOT: dmfc1 $4
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips64.txt | 17 # CHECK: dmfc1 $2, $f14
|
| mips64_le.txt | 14 # CHECK: dmfc1 $2, $f14
|
| mips64r2.txt | 14 # CHECK: dmfc1 $2, $f14
|
| mips64r2_le.txt | 14 # CHECK: dmfc1 $2, $f14
|
| /external/pixman/pixman/ |
| loongson-mmintrin.h | 20 * dmfc1 t9,$f9
23 * dmfc1 s0,$f19
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 20 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 22 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 22 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 24 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 24 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 24 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 59 dmfc1 $12,$f13
|
| /external/chromium_org/v8/src/mips64/ |
| disasm-mips64.cc | 484 case DMFC1:
485 Format(instr, "dmfc1 'rt, 'fs");
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-mips64.cc | 374 __ dmfc1(a6, f5);
823 __ dmfc1(a7, f31);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrFPU.td | 373 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 61 dmfc1 $12,$f13
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 61 dmfc1 $12,$f13
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 66 dmfc1 $12,$f13
|
