| /external/valgrind/main/none/tests/mips64/ |
| shift_instructions.stdout.exp-mips64r2 | 0 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
2 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
3 drotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
4 drotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
5 drotr $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
6 drotr $t2, $t3, 0x1f :: rt 0x257ad5400000000, rs 0x12bd6aa, imm 0x001f
7 drotr $a0, $a1, 0x0f :: rt 0xad54000000000257, rs 0x12bd6aa, imm 0x000f
8 drotr $s0, $s1, 0x03 :: rt 0x4000000000257ad5, rs 0x12bd6aa, imm 0x0003
9 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
10 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001
[all...] |
| rotate_swap.c | 56 printf("--- DROTR ---\n");
57 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 16);
58 TESTINST_DROTR("drotr", 0xffff0000ffffffff, 16);
59 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 8);
60 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 4);
61 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 5);
62 TESTINST_DROTR("drotr", 0x31415927ffffffff, 10);
63 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 4);
64 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 0);
65 TESTINST_DROTR("drotr", 0xeeeeffffffffffff, 16)
[all...] |
| rotate_swap.stdout.exp-mips64r2 | 1 --- DROTR ---
2 drotr :: in 0x2000ffffffffffff, out 0xffff2000ffffffff, SA 16
3 drotr :: in 0xffff0000ffffffff, out 0xffffffff0000ffff, SA 16
4 drotr :: in 0x2000ffffffffffff, out 0xff2000ffffffffff, SA 8
5 drotr :: in 0x2000ffffffffffff, out 0xf2000fffffffffff, SA 4
6 drotr :: in 0x2000ffffffffffff, out 0xf90007ffffffffff, SA 5
7 drotr :: in 0x31415927ffffffff, out 0xffcc505649ffffff, SA 10
8 drotr :: in 0x2000ffffffffffff, out 0xf2000fffffffffff, SA 4
9 drotr :: in 0x2000ffffffffffff, out 0x2000ffffffffffff, SA 0
10 drotr :: in 0xeeeeffffffffffff, out 0xffffeeeeffffffff, SA 1
[all...] |
| shift_instructions.c | 6 DROTR=0, DROTR32, DROTRV, DSLL,
18 for (op = DROTR; op <= SRLV; op++) {
21 case DROTR:
24 TEST2("drotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
25 TEST2("drotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
26 TEST2("drotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
27 TEST2("drotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
28 TEST2("drotr $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
29 TEST2("drotr $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
30 TEST2("drotr $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1)
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| mips64shift.ll | 88 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
97 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 9 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/ |
| mips_directives.s | 74 # CHECK: drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba]
76 drotr $9, $6, 30
|
| mips64-alu-instructions.s | 76 # CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00]
101 drotr $9, $6, 20
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips64.cc | 501 COMPARE(drotr(a0, a1, 0),
502 "0025203a drotr a0, a1, 0");
503 COMPARE(drotr(s0, s1, 8),
504 "0031823a drotr s0, s1, 8");
505 COMPARE(drotr(a6, a7, 24),
506 "002b563a drotr a6, a7, 24");
507 COMPARE(drotr(v0, v1, 31),
508 "002317fa drotr v0, v1, 31");
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 14 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips64r2.txt | 86 # CHECK: drotr $20, $27, 6
|
| mips64r2_le.txt | 86 # CHECK: drotr $20, $27, 6
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 71 drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa]
72 drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa]
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 79 case Mips::DROTR:
160 case Mips::DROTR:
|
| /external/llvm/lib/Target/Mips/ |
| Mips64InstrInfo.td | 129 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
|
| /external/chromium_org/v8/src/mips64/ |
| constants-mips64.h | 428 // drotr in special4?
|
| assembler-mips64.h | 807 void drotr(Register rd, Register rt, uint16_t sa);
[all...] |
| disasm-mips64.cc | 705 Format(instr, "drotr 'rd, 'rt, 'sa");
[all...] |
| assembler-mips64.cc | 1739 void Assembler::drotr(Register rd, Register rt, uint16_t sa) { function in class:v8::Assembler
[all...] |
| macro-assembler-mips64.cc | 1035 drotr(rd, rs, rt.imm64_);
[all...] |
| /external/qemu/target-mips/ |
| translate.c | 138 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
[all...] |
| /external/qemu/disas/ |
| mips.c | [all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_mips_toIR.c | [all...] |
| /prebuilts/android-emulator/linux-x86_64/ |
| emulator-mips | |
| /prebuilts/sdk/tools/linux/ |
| libLLVM.so | |
