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  /art/compiler/utils/mips/
assembler_mips.h 61 void Addi(Register rt, Register rs, uint16_t imm16);
62 void Addiu(Register rt, Register rs, uint16_t imm16);
71 void Andi(Register rt, Register rs, uint16_t imm16);
73 void Ori(Register rt, Register rs, uint16_t imm16);
75 void Xori(Register rt, Register rs, uint16_t imm16);
85 void Lb(Register rt, Register rs, uint16_t imm16);
86 void Lh(Register rt, Register rs, uint16_t imm16);
87 void Lw(Register rt, Register rs, uint16_t imm16);
88 void Lbu(Register rt, Register rs, uint16_t imm16);
89 void Lhu(Register rt, Register rs, uint16_t imm16);
    [all...]
assembler_mips.cc 170 void MipsAssembler::Addi(Register rt, Register rs, uint16_t imm16) {
171 EmitI(0x8, rs, rt, imm16);
174 void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) {
175 EmitI(0x9, rs, rt, imm16);
206 void MipsAssembler::Andi(Register rt, Register rs, uint16_t imm16) {
207 EmitI(0xc, rs, rt, imm16);
214 void MipsAssembler::Ori(Register rt, Register rs, uint16_t imm16) {
215 EmitI(0xd, rs, rt, imm16);
222 void MipsAssembler::Xori(Register rt, Register rs, uint16_t imm16) {
223 EmitI(0xe, rs, rt, imm16);
    [all...]
  /external/ltrace/sysdeps/linux-gnu/aarch64/
arch.h 24 * | 1 1 0 1 0 1 0 0 0 0 1 | imm16 | 0 0 0 0 0 | */
trace.c 41 * | 1 1 0 1 0 1 0 0 | 0 0 0 | imm16 | 0 0 0 0 1 | */
  /external/valgrind/main/none/tests/x86/
insn_basic.def 35 adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
36 adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
37 adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
38 adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
39 adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
40 adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
68 addw imm16[1234] ax.uw[5678] => 1.uw[6912]
69 addw imm16[1234] bx.uw[5678] => 1.uw[6912]
70 addw imm16[1234] m16.uw[5678] => 1.uw[6912]
88 andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230
    [all...]
  /art/compiler/dex/quick/mips/
mips_lir.h 394 kMipsAddiu, // addiu t,s,imm16 [001001] s[25..21] t[20..16] imm16[15..0].
397 kMipsAndi, // andi t,s,imm16 [001100] s[25..21] t[20..16] imm16[15..0].
417 kMipsLahi, // lui t,imm16 [00111100000] t[20..16] imm16[15..0] load addr hi.
418 kMipsLalo, // ori t,s,imm16 [001001] s[25..21] t[20..16] imm16[15..0] load addr lo.
419 kMipsLui, // lui t,imm16 [00111100000] t[20..16] imm16[15..0]
    [all...]
  /external/llvm/lib/Target/Mips/
Mips16InstrInfo.td 41 FI16<op, (outs), (ins brtarget:$imm16),
42 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
138 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
139 !strconcat(asmstr, "\t$imm16"),[], itin>;
    [all...]
Mips16InstrFormats.td 436 bits<16> imm16;
441 let Inst{26-21} = imm16{10-5};
442 let Inst{20-16} = imm16{15-11};
445 let Inst{4-0} = imm16{4-0};
487 bits<16> imm16;
493 let Inst{26-21} = imm16{10-5};
494 let Inst{20-16} = imm16{15-11};
498 let Inst{4-0} = imm16{4-0};
512 bits<16> imm16;
518 let Inst{26-21} = imm16{10-5}
    [all...]
MicroMipsInstrFormats.td 102 bits<16> imm16;
109 let Inst{15-0} = imm16;
115 bits<16> imm16;
122 let Inst{15-0} = imm16;
127 bits<16> imm16;
134 let Inst{15-0} = imm16;
435 bits<16> imm16;
442 let Inst{15-0} = imm16;
MipsInstrFormats.td 158 bits<16> imm16;
164 let Inst{15-0} = imm16;
173 bits<16> imm16;
179 let Inst{15-0} = imm16;
233 bits<16> imm16;
240 let Inst{15-0} = imm16;
303 bits<16> imm16;
310 let Inst{15-0} = imm16;
368 bits<16> imm16;
375 let Inst{15-0} = imm16;
    [all...]
  /external/valgrind/main/none/tests/amd64/
insn_basic.def 15 ###adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
16 ###adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
17 adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
18 adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
19 adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
20 adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
62 addw imm16[1234] ax.uw[5678] => 1.uw[6912]
63 addw imm16[1234] bx.uw[5678] => 1.uw[6912]
64 addw imm16[1234] m16.uw[5678] => 1.uw[6912]
89 andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64ExpandPseudoInsts.cpp 104 const unsigned Imm16 = getChunk(UImm, ChunkIdx);
111 .addImm(Imm16)
174 uint64_t Imm16 = 0;
177 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
179 if (Imm16 != ChunkVal)
189 .addImm(Imm16)
202 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
204 if (Imm16 != ChunkVal)
213 .addImm(Imm16)
521 unsigned Imm16 = (Imm >> Shift) & Mask
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcInstr64Bit.td 350 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
351 !strconcat(OpcStr, " $rs1, $imm16"), []>;
352 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
353 !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
354 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
355 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
356 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
357 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
361 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
362 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>
    [all...]
SparcInstrFormats.td 83 bits<16> imm16;
92 let Inst{21-20} = imm16{15-14};
95 let Inst{13-0} = imm16{13-0};
  /external/chromium_org/v8/src/x87/
assembler-x87.cc 434 void Assembler::mov_w(const Operand& dst, int16_t imm16) {
439 EMIT(static_cast<int8_t>(imm16 & 0xff));
440 EMIT(static_cast<int8_t>(imm16 >> 8));
671 void Assembler::cmpw(const Operand& op, Immediate imm16) {
672 DCHECK(imm16.is_int16());
677 emit_w(imm16);
1191 void Assembler::ret(int imm16) {
1193 DCHECK(is_uint16(imm16));
1194 if (imm16 == 0) {
1198 EMIT(imm16 & 0xFF)
    [all...]
  /art/compiler/utils/arm/
assembler_arm32.cc 676 void Arm32Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
679 B25 | B24 | ((imm16 >> 12) << 16) |
680 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
685 void Arm32Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
688 B25 | B24 | B22 | ((imm16 >> 12) << 16) |
689 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
    [all...]
assembler_arm32.h 84 void movw(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
85 void movt(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
128 void bkpt(uint16_t imm16) OVERRIDE;
assembler_thumb2.cc     [all...]
assembler_thumb2.h 106 void movw(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
107 void movt(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
153 void bkpt(uint16_t imm16) OVERRIDE;
  /external/valgrind/main/VEX/priv/
host_mips_defs.c 1005 MIPSRH *MIPSRH_Imm(Bool syned, UShort imm16)
1010 op->Mrh.Imm.imm16 = imm16;
1014 vassert(imm16 != 0x8000);
1033 vex_printf("%d", (Int) (Short) op->Mrh.Imm.imm16);
1035 vex_printf("%u", (UInt) (UShort) op->Mrh.Imm.imm16);
    [all...]
  /external/chromium_org/v8/src/ia32/
assembler-ia32.cc 492 void Assembler::mov_w(const Operand& dst, int16_t imm16) {
497 EMIT(static_cast<int8_t>(imm16 & 0xff));
498 EMIT(static_cast<int8_t>(imm16 >> 8));
738 void Assembler::cmpw(const Operand& op, Immediate imm16) {
739 DCHECK(imm16.is_int16());
744 emit_w(imm16);
1258 void Assembler::ret(int imm16) {
1260 DCHECK(is_uint16(imm16));
1261 if (imm16 == 0) {
1265 EMIT(imm16 & 0xFF)
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCJITInfo.cpp 33 #define BUILD_ADDIS(RD,RS,IMM16) \
34 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
50 #define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16)
  /external/chromium_org/v8/src/mips/
constants-mips.cc 290 // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16.
  /external/chromium_org/v8/src/mips64/
constants-mips64.cc 307 // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16.
  /external/vixl/src/a64/
macro-assembler-a64.cc 331 uint64_t imm16 = (imm >> (16 * i)) & 0xffff; local
332 if (imm16 != ignored_halfword) {
335 movn(temp, ~imm16 & 0xffff, 16 * i);
337 movz(temp, imm16, 16 * i);
342 movk(temp, imm16, 16 * i);
    [all...]

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