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  /external/chromium_org/third_party/webrtc/common_audio/signal_processing/
min_max_operations_mips.c 99 "movn %[totMax], %[tmp32_0], %[tmp32_1] \n\t"
124 "movn %[totMax], %[tmp32_0], %[r] \n\t"
126 "movn %[totMax], %[tmp32_1], %[r1] \n\t"
128 "movn %[totMax], %[tmp32_2], %[r2] \n\t"
130 "movn %[totMax], %[tmp32_3], %[r3] \n\t"
143 "movn %[totMax], %[tmp32_0], %[r] \n\t"
145 "movn %[totMax], %[tmp32_1], %[r1] \n\t"
147 "movn %[totMax], %[tmp32_2], %[r2] \n\t"
149 "movn %[totMax], %[tmp32_3], %[r3] \n\t"
162 "movn %[totMax], %[tmp32_0], %[r] \n\t
    [all...]
filter_ar_fast_q12_mips.c 74 "movn %[r0], %[max16], %[r1] \n\t"
76 "movn %[r0], %[min16], %[r1] \n\t"
117 "movn %[r0], %[max16], %[r1] \n\t"
119 "movn %[r0], %[min16], %[r1] \n\t"
complex_fft_mips.c 189 "movn %[tmp1], %[tmp6], %[tmp5] \n\t"
192 "movn %[tmp2], %[tmp6], %[tmp5] \n\t"
195 "movn %[tmp3], %[tmp6], %[tmp5] \n\t"
198 "movn %[tmp4], %[tmp6], %[tmp5] \n\t"
201 "movn %[tempMax], %[tmp1], %[tmp5] \n\t"
204 "movn %[tempMax], %[tmp2], %[tmp5] \n\t"
206 "movn %[tempMax], %[tmp3], %[tmp5] \n\t"
208 "movn %[tempMax], %[tmp4], %[tmp5] \n\t"
  /external/llvm/test/CodeGen/AArch64/
movw-consts.ll 52 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
56 ; CHECK: movn w0, #{{60875|0xedcb}}
62 ; CHECK: movn x0, #0
68 ; CHECK: movn x0, #{{60875|0xedcb}}, lsl #16
113 ; CHECK: movn {{w[0-9]+}}, #0
121 ; Mustn't MOVN w0 here.
arm64-icmp-opt.ll 11 ; CHECK-NOT: movn
arm64-variadic-aapcs.ll 35 ; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x37
73 ; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x27
76 ; CHECK: movn [[VR_OFFS:w[0-9]+]], #0x6f
arm64-movi.ll 76 ; Tests for MOVN with MOVK.
79 define i64 @movn() nounwind {
80 ; CHECK-LABEL: movn:
81 ; CHECK: movn x0, #0x29
87 ; CHECK: movn x0, #0x29, lsl #32
  /external/llvm/test/MC/AArch64/
elf-reloc-movw.s 17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
tls-relocs.s 7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
13 // CHECK: movn x2, #:dtprel_g2:var // encoding: [0bAAA00010,A,0b110AAAAA,0x92]
17 // CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
29 movn x6, #:dtprel_g1:var
31 movn w8, #:dtprel_g1:var
35 // CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
39 // CHECK: movn w8, #:dtprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12]
61 movn x12, #:dtprel_g0:var
63 movn w14, #:dtprel_g0:va
    [all...]
arm64-tls-relocs.s 44 movn x4, #:tprel_g2:var
47 // CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
55 movn x6, #:tprel_g1:var
59 // CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
81 movn x12, #:tprel_g0:var
85 // CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
168 movn x4, #:dtprel_g2:var
171 // CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
179 movn x6, #:dtprel_g1:var
183 // CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92
    [all...]
  /external/valgrind/main/none/tests/mips64/
move_instructions.c 242 printf("--- MOVN.S ---\n");
243 TEST4("movn.s $f0, $f2, $11", 0, 0, f0, f2, 11);
244 TEST4("movn.s $f0, $f2, $11", 0, 1, f0, f2, 11);
245 TEST4("movn.s $f0, $f2, $11", 8, 0xffff, f0, f2, 11);
246 TEST4("movn.s $f0, $f2, $11", 16, -1, f0, f2, 11);
247 TEST4("movn.s $f0, $f2, $11", 16, 5, f0, f2, 11);
248 TEST4("movn.s $f0, $f2, $11", 24, 0, f0, f2, 11);
249 TEST4("movn.s $f0, $f2, $11", 24, 0, f0, f2, 11);
250 TEST4("movn.s $f0, $f2, $11", 32, 5, f0, f2, 11);
251 TEST4("movn.s $f0, $f2, $11", 32, 125487, f0, f2, 11)
    [all...]
  /external/valgrind/main/none/tests/mips32/
MoveIns.c 237 // movn.s fd, fs, rt
258 // movn.d fd, fs, rt
480 printf("MOVN.S\n");
481 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 0, 0, f0, f2, t3);
482 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 4, 1, f0, f2, t3);
483 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 8, 0xffff, f0, f2, t3);
484 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 12, -1, f0, f2, t3);
485 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 16, 5, f0, f2, t3);
486 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 20, 0, f0, f2, t3);
487 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 24, 0, f0, f2, t3)
    [all...]
MoveIns.stdout.exp 192 MOVN.S
193 movn.s $f0, $f2, $t3 :: fs rt 0x0
194 movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
195 movn.s $f0, $f2, $t3 :: fs rt 0x40400000
196 movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
197 movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
198 movn.s $f0, $f2, $t3 :: fs rt 0x0
199 movn.s $f0, $f2, $t3 :: fs rt 0x0
200 movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
201 movn.s $f0, $f2, $t3 :: fs rt 0x44db000
    [all...]
MoveIns.stdout.exp-BE 192 MOVN.S
193 movn.s $f0, $f2, $t3 :: fs rt 0x0
194 movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
195 movn.s $f0, $f2, $t3 :: fs rt 0x40400000
196 movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
197 movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
198 movn.s $f0, $f2, $t3 :: fs rt 0x0
199 movn.s $f0, $f2, $t3 :: fs rt 0x0
200 movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
201 movn.s $f0, $f2, $t3 :: fs rt 0x44db000
    [all...]
  /external/llvm/test/CodeGen/Mips/
zeroreg.ll 16 ; 32-CMOV: movn $2, $zero, $4
22 ; 64-CMOV: movn $2, $zero, $4
63 ; 32-CMOV-DAG: movn $[[R0]], $zero, $4
64 ; 32-CMOV-DAG: movn $[[R1]], $zero, $4
73 ; 64-CMOV: movn $2, $zero, $4
  /external/llvm/test/MC/Mips/mips32r6/
invalid-mips32.s 15 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/llvm/lib/Target/Mips/
MipsCondMov.td 118 def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
122 def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
124 def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
126 def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
138 def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
142 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
149 def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
156 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
161 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,
  /external/chromium_org/v8/test/cctest/
test-disasm-mips.cc 467 COMPARE(movn(a0, a1, a2),
468 "00a6200b movn a0, a1, a2");
469 COMPARE(movn(s0, s1, s2),
470 "0232800b movn s0, s1, s2");
471 COMPARE(movn(t2, t3, t4),
472 "016c500b movn t2, t3, t4");
473 COMPARE(movn(v0, v1, a2),
474 "0066100b movn v0, v1, a2");
  /system/core/libpixelflinger/arch-mips/
t32cb16blend.S 79 DBG movn $v0,$t8,$at
81 DBG movn $v1,$t8,$at
166 DBG movn $v0,$t8,$at
168 DBG movn $v1,$t8,$at
  /external/llvm/test/MC/Mips/
micromips-movcond-instructions.s 13 # CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
20 # CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
24 movn $9, $6, $7
  /external/llvm/test/MC/Mips/mips2/
invalid-mips32.s 28 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/llvm/test/MC/Mips/mips3/
invalid-mips4.s 18 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
invalid-mips5.s 19 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/chromium_org/third_party/webrtc/modules/audio_processing/ns/
nsx_core_mips.c 67 "movn %[r6], %[r7], %[r4] \n\t"
79 "movn %[r0], $0, %[r6] \n\t"
267 "movn %[r7], %[r8], %[r9] \n\t"
274 "movn %[r2], %[const_neg8], %[r5] \n\t"
288 "movn %[r6], %[r5], %[r2] \n\t"
294 "movn %[r4], %[r5], %[r8] \n\t"
311 "movn %[r2], %[r5], %[r4] \n\t"
590 "movn %[r0], %[sat_neg], %[r1] \n\t"
591 "movn %[r2], %[sat_neg], %[r3] \n\t"
592 "movn %[r4], %[sat_neg], %[r5] \n\t
    [all...]
  /external/chromium_org/third_party/webrtc/modules/audio_coding/codecs/isac/fix/source/
transform_mips.c 101 "movn %[r4], %[r5], %[r0] \n\t"
103 "movn %[r6], %[r7], %[r1] \n\t"
105 "movn %[max], %[r4], %[r0] \n\t"
107 "movn %[max], %[r6], %[r1] \n\t"
160 "movn %[r1], %[r4], %[r3] \n\t"
175 "movn %[r0], %[r2], %[r3] \n\t"
178 "movn %[max], %[r1], %[r2] \n\t"
180 "movn %[max], %[r0], %[r2] \n\t"
    [all...]

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