| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| ret.ll | 10 ; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
11 ; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
12 ; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
151 ; NO-MTHC1-DAG: mtc1 $zero, $f0
153 ; MTHC1-DAG: mtc1 $zero, $f0
180 ; NO-MTHC1-DAG: mtc1 $zero, $f0
181 ; NO-MTHC1-DAG: mtc1 $zero, $f1
183 ; MTHC1-DAG: mtc1 $zero, $f0
184 ; MTHC1-DAG: mthc1 $zero, $f
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| 2013-11-18-fp64-const0.ll | 18 ; FIXME: A redundant mthc1 is currently emitted. Add a -NOT when it is
|
| buildpairextractelementf64.ll | 12 ; FP64-DAG: mthc1
|
| mno-ldc1-sdc1.ll | 63 ; 32R2-LE-PIC-DAG: mthc1 $[[R1]], $f0
68 ; 32R6-LE-PIC-DAG: mthc1 $[[R1]], $f0
82 ; 32R2-LE-STATIC-DAG: mthc1 $[[R3]], $f0
89 ; 32R6-LE-STATIC-DAG: mthc1 $[[R3]], $f0
99 ; 32R2-BE-PIC-DAG: mthc1 $[[R0]], $f0
104 ; 32R6-BE-PIC-DAG: mthc1 $[[R0]], $f0
197 ; 32R2-DAG: mthc1 $[[R1]], $f0
204 ; 32R6-DAG: mthc1 $[[R1]], $f0
|
| analyzebranch.ll | 17 ; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
|
| fcopysign.ll | 20 ; 32R2: mthc1 $[[INS]], $f0
|
| fmadd1.ll | 200 ; 32R2: mthc1 $zero, $[[T2]]
242 ; 32R2: mthc1 $zero, $[[T2]]
287 ; 32R2-NAN: mthc1 $zero, $[[T2]]
334 ; 32R2-NAN: mthc1 $zero, $[[T2]]
|
| select.ll | 174 ; 32R2-DAG: mthc1 $7, $[[F0]]
179 ; 32R6-DAG: mthc1 $7, $[[F0]]
471 ; 32R2-DAG: mthc1 $7, $[[F2]]
478 ; 32R6-DAG: mthc1 $7, $[[F2]]
|
| /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/ |
| SOURCES | 9 toolchain/binutils.git fff40e635995d00e3455f861a97d8cbf3ebb6b4e Merge "Add missing mtc1, mthc1, mfhc1 instructions to Ingenic's MXU patch."
|
| /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/ |
| SOURCES | 9 toolchain/binutils.git fff40e635995d00e3455f861a97d8cbf3ebb6b4e Merge "Add missing mtc1, mthc1, mfhc1 instructions to Ingenic's MXU patch."
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| simplestorefp1.ll | 32 ; CHECK: mthc1 $[[REG2a]], $f[[REG3]]
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 20 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /development/ndk/sources/android/libportable/arch-mips/ |
| _setjmp.S | 58 mthc1 t0, FPR ; \
|
| setjmp.S | 57 mthc1 t0, FPR ; \
|
| /external/llvm/lib/Target/Mips/ |
| MicroMipsInstrFPU.td | 128 def MTHC1_MM : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>,
|
| MipsSEInstrInfo.cpp | 553 // When mthc1 is available, use:
555 // mthc1 Hi, $fp
571 "MTHC1 requires MIPS32r2");
579 // MTHC1 is one of two instructions that are affected since they are
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 20 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 29 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 33 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| basic_operations_float.ll | 195 ; MIPS32-NOT: mthc1
216 ; MIPS32-NOT: mthc1
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 51 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/ |
| mips-fpu-instructions.s | 173 # CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
208 mthc1 $17, $f6
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 110 mthc1 $zero,$f16
|
| /external/chromium_org/v8/src/mips/ |
| macro-assembler-mips.cc | [all...] |
| disasm-mips.cc | 475 case MTHC1:
476 Format(instr, "mthc1 'rt, 'fs");
[all...] |
