/external/llvm/test/Transforms/InstCombine/ |
addnegneg.ll | 8 %sub4 = add i32 %c.neg, %b.neg ; <i32> [#uses=1] 9 %sub6 = add i32 %sub4, %d ; <i32> [#uses=1]
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/external/smali/dexlib2/src/test/java/org/jf/dexlib2/analysis/ |
CommonSuperclassTest.java | 80 TestUtils.makeInterfaceDef("Liface/sub4;", "Liface/base1;", "Liface/sub3;"), 84 TestUtils.makeClassDef("Liface/classsub4;", "Ljava/lang/Object;", "Liface/sub3;", "Liface/sub4;"), 87 "Liface/sub3;", "Liface/sub4;") 190 String sub4 = "Liface/sub4;"; local 209 superclassTest(base1, base1, sub4); 233 superclassTest(sub4, sub4, classsub4); 243 superclassTest(sub4, sub4, classsub1234) [all...] |
/external/clang/test/Sema/ |
typecheck-binop.c | 17 int sub4(void *P, void *Q) { function
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/cts/suite/audio_quality/test/ |
StringUtilTest.cpp | 43 android::String8 sub4 = StringUtil::substr(str, 100, 5); local 44 ASSERT_TRUE(sub4.length() == 0);
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/external/llvm/test/Transforms/Reassociate/ |
pr12245.ll | 25 %sub4 = sub nsw i32 %dec3, %5 26 store i32 %sub4, i32* @d, align 4
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/external/llvm/test/Transforms/SLPVectorizer/X86/ |
phi3.ll | 22 %sub4 = fsub double %sub1, undef 23 %div.i16 = fdiv double %sub4, undef
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/external/llvm/test/CodeGen/Mips/ |
stldst.ll | 26 %sub4 = add nsw i32 %5, -5 33 %call7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind
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/external/llvm/test/CodeGen/X86/ |
2011-03-02-DAGCombiner.ll | 36 %sub4 = fsub x86_fp80 %conv3, %tmp1 37 %conv5 = fptoui x86_fp80 %sub4 to i32
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haddsub-2.ll | 63 %sub4 = fsub float %vecext2, %vecext3 64 %vecinit5 = insertelement <4 x float> %vecinit, float %sub4, i32 1 87 %sub4 = fsub float %vecext2, %vecext3 88 %vecinit5 = insertelement <4 x float> %vecinit, float %sub4, i32 0 165 %sub4 = sub i32 %vecext2, %vecext3 166 %vecinit5 = insertelement <4 x i32> %vecinit, i32 %sub4, i32 1 192 %sub4 = sub i32 %vecext2, %vecext3 193 %vecinit5 = insertelement <4 x i32> %vecinit, i32 %sub4, i32 0 314 %sub4 = fsub double %vecext2, %vecext3 315 %vecinit5 = insertelement <4 x double> %vecinit, double %sub4, i32 [all...] |
atomic_add.ll | 128 define void @sub4(i64* nocapture %p, i32 %v) nounwind ssp { 130 ; CHECK-LABEL: sub4:
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sse3-avx-addsub-2.ll | 188 %sub4 = fsub float %11, %12 202 %vecinsert8 = insertelement <8 x float> %vecinsert7, float %sub4, i32 6
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/external/chromium_org/third_party/sfntly/cpp/src/test/ |
bitmap_table_test.cc | 168 IndexSubTableFormat4Ptr sub4 = local 170 EXPECT_FALSE(sub4 == NULL); 190 info.Attach(sub4->GlyphInfo(i));
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/external/sfntly/cpp/src/test/ |
bitmap_table_test.cc | 168 IndexSubTableFormat4Ptr sub4 = local 170 EXPECT_FALSE(sub4 == NULL); 190 info.Attach(sub4->GlyphInfo(i));
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/external/llvm/lib/Target/R600/ |
SIRegisterInfo.td | 67 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7], 78 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, 120 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7], 131 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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AMDGPURegisterInfo.cpp | 51 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
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/external/llvm/test/CodeGen/SystemZ/ |
fp-sub-01.ll | 110 %sub4 = fsub float %sub3, %val4 111 %sub5 = fsub float %sub4, %val5
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fp-sub-02.ll | 110 %sub4 = fsub double %sub3, %val4 111 %sub5 = fsub double %sub4, %val5
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int-sub-04.ll | 132 %sub4 = sub i64 %sub3, %val4 133 %sub5 = sub i64 %sub4, %val5
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int-sub-01.ll | 167 %sub4 = sub i32 %sub3, %val4 168 %sub5 = sub i32 %sub4, %val5
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int-sub-02.ll | 172 %sub4 = sub i64 %sub3, %ext4 173 %sub5 = sub i64 %sub4, %ext5
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int-sub-03.ll | 172 %sub4 = sub i64 %sub3, %ext4 173 %sub5 = sub i64 %sub4, %ext5
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int-sub-05.ll | 149 %sub4 = sub i128 %sub3, %val4 150 store i128 %sub4, i128 *%retptr
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
SIGenRegisterInfo.pl | 37 def sub4 : SubRegIndex; 59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 181 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
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/external/mesa3d/src/gallium/drivers/radeon/ |
SIGenRegisterInfo.pl | 37 def sub4 : SubRegIndex; 59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 181 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
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/external/llvm/test/Transforms/LoopVectorize/ |
global_alias.ll | 584 %sub4 = sub nsw i32 %sub3, 1 587 %arrayidx6 = getelementptr inbounds [100 x i32]* %arrayidx5, i32 0, i32 %sub4 644 %sub4 = sub nsw i32 100, %5 645 %sub5 = sub nsw i32 %sub4, 1 [all...] |