| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_wm_pass1.c | 42 if (inst->writemask & (1<<i)) {
44 inst->writemask &= ~(1<<i);
50 return inst->writemask;
123 GLuint writemask; local
144 writemask = get_tracked_mask(c, inst);
145 if (!writemask) {
166 read0 = writemask;
180 read0 = writemask;
181 read1 = writemask;
186 read0 = writemask;
[all...] |
| gen6_depthstencil.c | 60 ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
73 ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
79 if (ctx->Stencil.WriteMask[0] ||
80 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
|
| brw_wm_pass0.c | 247 GLuint writemask )
253 if (writemask & (1<<i)) {
259 out->writemask = writemask;
317 GLuint writemask = inst->DstReg.WriteMask; local
341 pass0_set_dst(c, out, inst, writemask);
353 GLuint writemask = inst->DstReg.WriteMask; local
368 if (writemask & (1 << i)) {
[all...] |
| brw_wm_debug.c | 101 if (inst->writemask != WRITEMASK_XYZW)
103 GET_BIT(inst->writemask, 0) ? "x" : "",
104 GET_BIT(inst->writemask, 1) ? "y" : "",
105 GET_BIT(inst->writemask, 2) ? "z" : "",
106 GET_BIT(inst->writemask, 3) ? "w" : "");
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_wm_pass1.c | 42 if (inst->writemask & (1<<i)) {
44 inst->writemask &= ~(1<<i);
50 return inst->writemask;
123 GLuint writemask; local
144 writemask = get_tracked_mask(c, inst);
145 if (!writemask) {
166 read0 = writemask;
180 read0 = writemask;
181 read1 = writemask;
186 read0 = writemask;
[all...] |
| gen6_depthstencil.c | 60 ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
73 ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
79 if (ctx->Stencil.WriteMask[0] ||
80 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
|
| brw_wm_pass0.c | 247 GLuint writemask )
253 if (writemask & (1<<i)) {
259 out->writemask = writemask;
317 GLuint writemask = inst->DstReg.WriteMask; local
341 pass0_set_dst(c, out, inst, writemask);
353 GLuint writemask = inst->DstReg.WriteMask; local
368 if (writemask & (1 << i)) {
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/tests/ |
| rc_test_helpers.c | 203 struct match_info WriteMask;
236 tokens.WriteMask.String = dst_str + matches[3].rm_so;
237 tokens.WriteMask.Length = match_length(matches, 3);
258 /* WriteMask */
259 if (tokens.WriteMask.Length == 0) {
260 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
263 if (tokens.WriteMask.String[0] != '.') {
264 fprintf(stderr, "1st char of writemask is not valid.\n");
267 for (i = 1; i < tokens.WriteMask.Length; i++) {
268 switch(tokens.WriteMask.String[i])
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| rc_test_helpers.c | 203 struct match_info WriteMask;
236 tokens.WriteMask.String = dst_str + matches[3].rm_so;
237 tokens.WriteMask.Length = match_length(matches, 3);
258 /* WriteMask */
259 if (tokens.WriteMask.Length == 0) {
260 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
263 if (tokens.WriteMask.String[0] != '.') {
264 fprintf(stderr, "1st char of writemask is not valid.\n");
267 for (i = 1; i < tokens.WriteMask.Length; i++) {
268 switch(tokens.WriteMask.String[i])
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/ |
| i915_fpc_optimize.c | 121 * of writemask which are set, swizzle to identity otherwise.
165 o->WriteMask = i->WriteMask;
210 is_unswizzled(¤t->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) &&
211 is_unswizzled(¤t->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) &&
212 is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) )
218 next->FullInstruction.Dst[0].Register.WriteMask,
221 current->FullInstruction.Dst[0].Register.WriteMask = current->FullInstruction.Dst[0].Register.WriteMask |
222 next->FullInstruction.Dst[0].Register.WriteMask;
[all...] |
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_optimize.c | 121 * of writemask which are set, swizzle to identity otherwise.
165 o->WriteMask = i->WriteMask;
210 is_unswizzled(¤t->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) &&
211 is_unswizzled(¤t->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) &&
212 is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) )
218 next->FullInstruction.Dst[0].Register.WriteMask,
221 current->FullInstruction.Dst[0].Register.WriteMask = current->FullInstruction.Dst[0].Register.WriteMask |
222 next->FullInstruction.Dst[0].Register.WriteMask;
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/docs/source/cso/ |
| dsa.rst | 23 writemask
40 writemask
41 Stencil test writemask; this controls which bits of the stencil buffer
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_rename_regs.c | 72 unsigned writemask; local
86 writemask = rc_variable_writemask_sum(var);
87 rc_variable_change_dst(var, new_index, writemask);
|
| radeon_variable.c | 38 * Rewrite the index and writemask for the destination register of var
60 if (var_ptr->Dst.WriteMask == RC_MASK_W) {
156 unsigned int mask = var->Readers[i].WriteMask;
285 new->Dst.WriteMask = DstWriteMask;
320 unsigned int writemask; local
332 if (sub_inst->WriteMask) {
334 writemask = sub_inst->WriteMask;
337 writemask = sub_inst->OutputWriteMask;
339 writemask = 0
392 unsigned int writemask = 0; local
[all...] |
| radeon_pair_regalloc.c | 57 unsigned int Writemask;
238 unsigned int writemask,
248 if (classes[i].Writemasks[j] == writemask) {
281 unsigned int writemask = rc_variable_writemask_sum(variable); local
293 writemask = RC_MASK_XYZW;
299 class_index = find_class(classes, writemask, 3);
314 writemask, c.Writemasks[i]);
321 * then the writemask will be set to RC_MASK_XYZW
379 class_index = find_class(classes, writemask,
388 variable->Dst.Index, writemask);
615 unsigned int chan, class_id, writemask = 0; local
692 unsigned int writemask = reg_get_writemask(reg); local
[all...] |
| radeon_pair_translate.c | 90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0;
91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0;
275 inst->DstReg.WriteMask);
286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
293 inst->DstReg.WriteMask & RC_MASK_XYZ;
295 GET_BIT(inst->DstReg.WriteMask, 3);
303 pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ;
307 pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask, 3) << 3)
[all...] |
| /external/mesa3d/src/gallium/docs/source/cso/ |
| dsa.rst | 23 writemask
40 writemask
41 Stencil test writemask; this controls which bits of the stencil buffer
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_rename_regs.c | 72 unsigned writemask; local
86 writemask = rc_variable_writemask_sum(var);
87 rc_variable_change_dst(var, new_index, writemask);
|
| radeon_variable.c | 38 * Rewrite the index and writemask for the destination register of var
60 if (var_ptr->Dst.WriteMask == RC_MASK_W) {
156 unsigned int mask = var->Readers[i].WriteMask;
285 new->Dst.WriteMask = DstWriteMask;
320 unsigned int writemask; local
332 if (sub_inst->WriteMask) {
334 writemask = sub_inst->WriteMask;
337 writemask = sub_inst->OutputWriteMask;
339 writemask = 0
392 unsigned int writemask = 0; local
[all...] |
| radeon_pair_regalloc.c | 57 unsigned int Writemask;
238 unsigned int writemask,
248 if (classes[i].Writemasks[j] == writemask) {
281 unsigned int writemask = rc_variable_writemask_sum(variable); local
293 writemask = RC_MASK_XYZW;
299 class_index = find_class(classes, writemask, 3);
314 writemask, c.Writemasks[i]);
321 * then the writemask will be set to RC_MASK_XYZW
379 class_index = find_class(classes, writemask,
388 variable->Dst.Index, writemask);
615 unsigned int chan, class_id, writemask = 0; local
692 unsigned int writemask = reg_get_writemask(reg); local
[all...] |
| radeon_pair_translate.c | 90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0;
91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0;
275 inst->DstReg.WriteMask);
286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
293 inst->DstReg.WriteMask & RC_MASK_XYZ;
295 GET_BIT(inst->DstReg.WriteMask, 3);
303 pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ;
307 pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask, 3) << 3)
[all...] |
| /external/chromium_org/third_party/skia/src/gpu/gl/ |
| GrGLPathRendering.cpp | 165 GrGLint writeMask = fHWPathStencilSettings.writeMask(GrStencilSettings::kFront_Face);
166 GL_CALL(StencilFillPath(id, fillMode, writeMask));
183 GrGLint writeMask = fHWPathStencilSettings.writeMask(GrStencilSettings::kFront_Face);
188 GL_CALL(StencilFillPath(id, fillMode, writeMask));
190 this->stencilThenCoverStrokePath(id, 0xffff, writeMask, GR_GL_BOUNDING_BOX);
192 this->stencilThenCoverFillPath(id, fillMode, writeMask, GR_GL_BOUNDING_BOX);
196 GL_CALL(StencilFillPath(id, fillMode, writeMask));
199 GL_CALL(StencilStrokePath(id, 0xffff, writeMask));
[all...] |
| /external/chromium_org/third_party/mesa/src/src/glx/ |
| pixel.c | 284 GLint writeMask, i;
317 writeMask = highBitMask;
320 /* Set up writeMask (to write to current byte) */
322 /* Need to trim writeMask */
323 writeMask &= HighBitsMask[bitOffset + elementsLeft];
335 currentByte = (currentByte & ~writeMask) |
336 (writeByte & writeMask);
340 currentByte = (currentByte & ~writeMask) |
341 (sourceImage[0] & writeMask);
359 writeMask = 0xff
[all...] |
| /external/mesa3d/src/glx/ |
| pixel.c | 284 GLint writeMask, i;
317 writeMask = highBitMask;
320 /* Set up writeMask (to write to current byte) */
322 /* Need to trim writeMask */
323 writeMask &= HighBitsMask[bitOffset + elementsLeft];
335 currentByte = (currentByte & ~writeMask) |
336 (writeByte & writeMask);
340 currentByte = (currentByte & ~writeMask) |
341 (sourceImage[0] & writeMask);
359 writeMask = 0xff
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/ |
| st_atom_depth.c | 107 dsa->depth.writemask = ctx->Depth.Mask;
118 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
129 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff;
|
