1 //===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // SI Intrinsic Definitions 11 // 12 //===----------------------------------------------------------------------===// 13 14 15 let TargetPrefix = "SI", isTarget = 1 in { 16 17 def int_SI_tid : Intrinsic <[llvm_i32_ty], [], [IntrNoMem]>; 18 def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 19 def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>; 20 def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; 21 def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ; 22 23 // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed 24 def int_SI_tbuffer_store : Intrinsic < 25 [], 26 [llvm_anyint_ty, // rsrc(SGPR) 27 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32 28 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW 29 llvm_i32_ty, // vaddr(VGPR) 30 llvm_i32_ty, // soffset(SGPR) 31 llvm_i32_ty, // inst_offset(imm) 32 llvm_i32_ty, // dfmt(imm) 33 llvm_i32_ty, // nfmt(imm) 34 llvm_i32_ty, // offen(imm) 35 llvm_i32_ty, // idxen(imm) 36 llvm_i32_ty, // glc(imm) 37 llvm_i32_ty, // slc(imm) 38 llvm_i32_ty], // tfe(imm) 39 []>; 40 41 // Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed 42 def int_SI_buffer_load_dword : Intrinsic < 43 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32 44 [llvm_anyint_ty, // rsrc(SGPR) 45 llvm_anyint_ty, // vaddr(VGPR) 46 llvm_i32_ty, // soffset(SGPR) 47 llvm_i32_ty, // inst_offset(imm) 48 llvm_i32_ty, // offen(imm) 49 llvm_i32_ty, // idxen(imm) 50 llvm_i32_ty, // glc(imm) 51 llvm_i32_ty, // slc(imm) 52 llvm_i32_ty], // tfe(imm) 53 [IntrReadArgMem]>; 54 55 def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 56 57 class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; 58 59 // Fully-flexible SAMPLE instruction. 60 class SampleRaw : Intrinsic < 61 [llvm_v4f32_ty], // vdata(VGPR) 62 [llvm_anyint_ty, // vaddr(VGPR) 63 llvm_v32i8_ty, // rsrc(SGPR) 64 llvm_v16i8_ty, // sampler(SGPR) 65 llvm_i32_ty, // dmask(imm) 66 llvm_i32_ty, // unorm(imm) 67 llvm_i32_ty, // r128(imm) 68 llvm_i32_ty, // da(imm) 69 llvm_i32_ty, // glc(imm) 70 llvm_i32_ty, // slc(imm) 71 llvm_i32_ty, // tfe(imm) 72 llvm_i32_ty], // lwe(imm) 73 [IntrNoMem]>; 74 75 def int_SI_sample : Sample; 76 def int_SI_sampleb : Sample; 77 def int_SI_sampled : Sample; 78 def int_SI_samplel : Sample; 79 80 // Basic gather4 81 def int_SI_gather4 : SampleRaw; 82 def int_SI_gather4_cl : SampleRaw; 83 def int_SI_gather4_l : SampleRaw; 84 def int_SI_gather4_b : SampleRaw; 85 def int_SI_gather4_b_cl : SampleRaw; 86 def int_SI_gather4_lz : SampleRaw; 87 88 // Gather4 with comparison 89 def int_SI_gather4_c : SampleRaw; 90 def int_SI_gather4_c_cl : SampleRaw; 91 def int_SI_gather4_c_l : SampleRaw; 92 def int_SI_gather4_c_b : SampleRaw; 93 def int_SI_gather4_c_b_cl : SampleRaw; 94 def int_SI_gather4_c_lz : SampleRaw; 95 96 // Gather4 with offsets 97 def int_SI_gather4_o : SampleRaw; 98 def int_SI_gather4_cl_o : SampleRaw; 99 def int_SI_gather4_l_o : SampleRaw; 100 def int_SI_gather4_b_o : SampleRaw; 101 def int_SI_gather4_b_cl_o : SampleRaw; 102 def int_SI_gather4_lz_o : SampleRaw; 103 104 // Gather4 with comparison and offsets 105 def int_SI_gather4_c_o : SampleRaw; 106 def int_SI_gather4_c_cl_o : SampleRaw; 107 def int_SI_gather4_c_l_o : SampleRaw; 108 def int_SI_gather4_c_b_o : SampleRaw; 109 def int_SI_gather4_c_b_cl_o : SampleRaw; 110 def int_SI_gather4_c_lz_o : SampleRaw; 111 112 def int_SI_getlod : SampleRaw; 113 114 def int_SI_imageload : Intrinsic <[llvm_v4i32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>; 115 116 def int_SI_resinfo : Intrinsic <[llvm_v4i32_ty], [llvm_i32_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>; 117 118 /* Interpolation Intrinsics */ 119 120 def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 121 def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>; 122 123 /* Control flow Intrinsics */ 124 125 def int_SI_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>; 126 def int_SI_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>; 127 def int_SI_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>; 128 def int_SI_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>; 129 def int_SI_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>; 130 def int_SI_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>; 131 def int_SI_end_cf : Intrinsic<[], [llvm_i64_ty], []>; 132 } 133
