1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2 ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 3 4 declare i32 @llvm.AMDGPU.bfe.u32(i32, i32, i32) nounwind readnone 5 6 ; FUNC-LABEL: @bfe_u32_arg_arg_arg 7 ; SI: V_BFE_U32 8 ; EG: BFE_UINT 9 define void @bfe_u32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { 10 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 %src1) nounwind readnone 11 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 12 ret void 13 } 14 15 ; FUNC-LABEL: @bfe_u32_arg_arg_imm 16 ; SI: V_BFE_U32 17 ; EG: BFE_UINT 18 define void @bfe_u32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { 19 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 123) nounwind readnone 20 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 21 ret void 22 } 23 24 ; FUNC-LABEL: @bfe_u32_arg_imm_arg 25 ; SI: V_BFE_U32 26 ; EG: BFE_UINT 27 define void @bfe_u32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind { 28 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 123, i32 %src2) nounwind readnone 29 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 30 ret void 31 } 32 33 ; FUNC-LABEL: @bfe_u32_imm_arg_arg 34 ; SI: V_BFE_U32 35 ; EG: BFE_UINT 36 define void @bfe_u32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind { 37 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 123, i32 %src1, i32 %src2) nounwind readnone 38 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 39 ret void 40 } 41 42 ; FUNC-LABEL: @bfe_u32_arg_0_width_reg_offset 43 ; SI-NOT: BFE 44 ; SI: S_ENDPGM 45 ; EG-NOT: BFE 46 define void @bfe_u32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { 47 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 0) nounwind readnone 48 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 49 ret void 50 } 51 52 ; FUNC-LABEL: @bfe_u32_arg_0_width_imm_offset 53 ; SI-NOT: BFE 54 ; SI: S_ENDPGM 55 ; EG-NOT: BFE 56 define void @bfe_u32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { 57 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 8, i32 0) nounwind readnone 58 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 59 ret void 60 } 61 62 ; FUNC-LABEL: @bfe_u32_zextload_i8 63 ; SI: BUFFER_LOAD_UBYTE 64 ; SI-NOT: BFE 65 ; SI: S_ENDPGM 66 define void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { 67 %load = load i8 addrspace(1)* %in 68 %ext = zext i8 %load to i32 69 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 8) 70 store i32 %bfe, i32 addrspace(1)* %out, align 4 71 ret void 72 } 73 74 ; FUNC-LABEL: @bfe_u32_zext_in_reg_i8 75 ; SI: BUFFER_LOAD_DWORD 76 ; SI: V_ADD_I32 77 ; SI-NEXT: V_AND_B32_e32 78 ; SI-NOT: BFE 79 ; SI: S_ENDPGM 80 define void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 81 %load = load i32 addrspace(1)* %in, align 4 82 %add = add i32 %load, 1 83 %ext = and i32 %add, 255 84 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 8) 85 store i32 %bfe, i32 addrspace(1)* %out, align 4 86 ret void 87 } 88 89 ; FUNC-LABEL: @bfe_u32_zext_in_reg_i16 90 ; SI: BUFFER_LOAD_DWORD 91 ; SI: V_ADD_I32 92 ; SI-NEXT: V_AND_B32_e32 93 ; SI-NOT: BFE 94 ; SI: S_ENDPGM 95 define void @bfe_u32_zext_in_reg_i16(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 96 %load = load i32 addrspace(1)* %in, align 4 97 %add = add i32 %load, 1 98 %ext = and i32 %add, 65535 99 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 16) 100 store i32 %bfe, i32 addrspace(1)* %out, align 4 101 ret void 102 } 103 104 ; FUNC-LABEL: @bfe_u32_zext_in_reg_i8_offset_1 105 ; SI: BUFFER_LOAD_DWORD 106 ; SI: V_ADD_I32 107 ; SI: BFE 108 ; SI: S_ENDPGM 109 define void @bfe_u32_zext_in_reg_i8_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 110 %load = load i32 addrspace(1)* %in, align 4 111 %add = add i32 %load, 1 112 %ext = and i32 %add, 255 113 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 1, i32 8) 114 store i32 %bfe, i32 addrspace(1)* %out, align 4 115 ret void 116 } 117 118 ; FUNC-LABEL: @bfe_u32_zext_in_reg_i8_offset_3 119 ; SI: BUFFER_LOAD_DWORD 120 ; SI: V_ADD_I32 121 ; SI-NEXT: V_AND_B32_e32 {{v[0-9]+}}, 0xf8 122 ; SI-NEXT: BFE 123 ; SI: S_ENDPGM 124 define void @bfe_u32_zext_in_reg_i8_offset_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 125 %load = load i32 addrspace(1)* %in, align 4 126 %add = add i32 %load, 1 127 %ext = and i32 %add, 255 128 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 3, i32 8) 129 store i32 %bfe, i32 addrspace(1)* %out, align 4 130 ret void 131 } 132 133 ; FUNC-LABEL: @bfe_u32_zext_in_reg_i8_offset_7 134 ; SI: BUFFER_LOAD_DWORD 135 ; SI: V_ADD_I32 136 ; SI-NEXT: V_AND_B32_e32 {{v[0-9]+}}, 0x80 137 ; SI-NEXT: BFE 138 ; SI: S_ENDPGM 139 define void @bfe_u32_zext_in_reg_i8_offset_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 140 %load = load i32 addrspace(1)* %in, align 4 141 %add = add i32 %load, 1 142 %ext = and i32 %add, 255 143 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 7, i32 8) 144 store i32 %bfe, i32 addrspace(1)* %out, align 4 145 ret void 146 } 147 148 ; FUNC-LABEL: @bfe_u32_zext_in_reg_i16_offset_8 149 ; SI: BUFFER_LOAD_DWORD 150 ; SI: V_ADD_I32 151 ; SI-NEXT: BFE 152 ; SI: S_ENDPGM 153 define void @bfe_u32_zext_in_reg_i16_offset_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 154 %load = load i32 addrspace(1)* %in, align 4 155 %add = add i32 %load, 1 156 %ext = and i32 %add, 65535 157 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 8, i32 8) 158 store i32 %bfe, i32 addrspace(1)* %out, align 4 159 ret void 160 } 161 162 ; FUNC-LABEL: @bfe_u32_test_1 163 ; SI: BUFFER_LOAD_DWORD 164 ; SI: V_AND_B32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} 165 ; SI: S_ENDPGM 166 ; EG: AND_INT T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, 1, 167 define void @bfe_u32_test_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 168 %x = load i32 addrspace(1)* %in, align 4 169 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 0, i32 1) 170 store i32 %bfe, i32 addrspace(1)* %out, align 4 171 ret void 172 } 173 174 define void @bfe_u32_test_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 175 %x = load i32 addrspace(1)* %in, align 4 176 %shl = shl i32 %x, 31 177 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 8) 178 store i32 %bfe, i32 addrspace(1)* %out, align 4 179 ret void 180 } 181 182 define void @bfe_u32_test_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 183 %x = load i32 addrspace(1)* %in, align 4 184 %shl = shl i32 %x, 31 185 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 1) 186 store i32 %bfe, i32 addrspace(1)* %out, align 4 187 ret void 188 } 189 190 ; FUNC-LABEL: @bfe_u32_test_4 191 ; SI-NOT: LSHL 192 ; SI-NOT: SHR 193 ; SI-NOT: BFE 194 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 195 ; SI: BUFFER_STORE_DWORD [[VREG]], 196 ; SI: S_ENDPGM 197 define void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 198 %x = load i32 addrspace(1)* %in, align 4 199 %shl = shl i32 %x, 31 200 %shr = lshr i32 %shl, 31 201 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shr, i32 31, i32 1) 202 store i32 %bfe, i32 addrspace(1)* %out, align 4 203 ret void 204 } 205 206 ; FUNC-LABEL: @bfe_u32_test_5 207 ; SI: BUFFER_LOAD_DWORD 208 ; SI-NOT: LSHL 209 ; SI-NOT: SHR 210 ; SI: V_BFE_I32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1 211 ; SI: S_ENDPGM 212 define void @bfe_u32_test_5(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 213 %x = load i32 addrspace(1)* %in, align 4 214 %shl = shl i32 %x, 31 215 %shr = ashr i32 %shl, 31 216 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shr, i32 0, i32 1) 217 store i32 %bfe, i32 addrspace(1)* %out, align 4 218 ret void 219 } 220 221 ; FUNC-LABEL: @bfe_u32_test_6 222 ; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} 223 ; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} 224 ; SI: S_ENDPGM 225 define void @bfe_u32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 226 %x = load i32 addrspace(1)* %in, align 4 227 %shl = shl i32 %x, 31 228 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 1, i32 31) 229 store i32 %bfe, i32 addrspace(1)* %out, align 4 230 ret void 231 } 232 233 ; FUNC-LABEL: @bfe_u32_test_7 234 ; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} 235 ; SI-NOT: BFE 236 ; SI: S_ENDPGM 237 define void @bfe_u32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 238 %x = load i32 addrspace(1)* %in, align 4 239 %shl = shl i32 %x, 31 240 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 31) 241 store i32 %bfe, i32 addrspace(1)* %out, align 4 242 ret void 243 } 244 245 ; FUNC-LABEL: @bfe_u32_test_8 246 ; SI-NOT: BFE 247 ; SI: V_AND_B32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} 248 ; SI-NOT: BFE 249 ; SI: S_ENDPGM 250 define void @bfe_u32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 251 %x = load i32 addrspace(1)* %in, align 4 252 %shl = shl i32 %x, 31 253 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1) 254 store i32 %bfe, i32 addrspace(1)* %out, align 4 255 ret void 256 } 257 258 ; FUNC-LABEL: @bfe_u32_test_9 259 ; SI-NOT: BFE 260 ; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} 261 ; SI-NOT: BFE 262 ; SI: S_ENDPGM 263 define void @bfe_u32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 264 %x = load i32 addrspace(1)* %in, align 4 265 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 31, i32 1) 266 store i32 %bfe, i32 addrspace(1)* %out, align 4 267 ret void 268 } 269 270 ; FUNC-LABEL: @bfe_u32_test_10 271 ; SI-NOT: BFE 272 ; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} 273 ; SI-NOT: BFE 274 ; SI: S_ENDPGM 275 define void @bfe_u32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 276 %x = load i32 addrspace(1)* %in, align 4 277 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 1, i32 31) 278 store i32 %bfe, i32 addrspace(1)* %out, align 4 279 ret void 280 } 281 282 ; FUNC-LABEL: @bfe_u32_test_11 283 ; SI-NOT: BFE 284 ; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}} 285 ; SI-NOT: BFE 286 ; SI: S_ENDPGM 287 define void @bfe_u32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 288 %x = load i32 addrspace(1)* %in, align 4 289 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 8, i32 24) 290 store i32 %bfe, i32 addrspace(1)* %out, align 4 291 ret void 292 } 293 294 ; FUNC-LABEL: @bfe_u32_test_12 295 ; SI-NOT: BFE 296 ; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}} 297 ; SI-NOT: BFE 298 ; SI: S_ENDPGM 299 define void @bfe_u32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 300 %x = load i32 addrspace(1)* %in, align 4 301 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 24, i32 8) 302 store i32 %bfe, i32 addrspace(1)* %out, align 4 303 ret void 304 } 305 306 ; FUNC-LABEL: @bfe_u32_test_13 307 ; V_ASHRREV_U32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}} 308 ; SI-NOT: BFE 309 ; SI: S_ENDPGM 310 define void @bfe_u32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 311 %x = load i32 addrspace(1)* %in, align 4 312 %shl = ashr i32 %x, 31 313 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1) 314 store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void 315 } 316 317 ; FUNC-LABEL: @bfe_u32_test_14 318 ; SI-NOT: LSHR 319 ; SI-NOT: BFE 320 ; SI: S_ENDPGM 321 define void @bfe_u32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 322 %x = load i32 addrspace(1)* %in, align 4 323 %shl = lshr i32 %x, 31 324 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1) 325 store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void 326 } 327 328 ; FUNC-LABEL: @bfe_u32_constant_fold_test_0 329 ; SI-NOT: BFE 330 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 331 ; SI: BUFFER_STORE_DWORD [[VREG]], 332 ; SI: S_ENDPGM 333 ; EG-NOT: BFE 334 define void @bfe_u32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind { 335 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 0) nounwind readnone 336 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 337 ret void 338 } 339 340 ; FUNC-LABEL: @bfe_u32_constant_fold_test_1 341 ; SI-NOT: BFE 342 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 343 ; SI: BUFFER_STORE_DWORD [[VREG]], 344 ; SI: S_ENDPGM 345 ; EG-NOT: BFE 346 define void @bfe_u32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind { 347 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 12334, i32 0, i32 0) nounwind readnone 348 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 349 ret void 350 } 351 352 ; FUNC-LABEL: @bfe_u32_constant_fold_test_2 353 ; SI-NOT: BFE 354 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 355 ; SI: BUFFER_STORE_DWORD [[VREG]], 356 ; SI: S_ENDPGM 357 ; EG-NOT: BFE 358 define void @bfe_u32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind { 359 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 1) nounwind readnone 360 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 361 ret void 362 } 363 364 ; FUNC-LABEL: @bfe_u32_constant_fold_test_3 365 ; SI-NOT: BFE 366 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 367 ; SI: BUFFER_STORE_DWORD [[VREG]], 368 ; SI: S_ENDPGM 369 ; EG-NOT: BFE 370 define void @bfe_u32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind { 371 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 1, i32 0, i32 1) nounwind readnone 372 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 373 ret void 374 } 375 376 ; FUNC-LABEL: @bfe_u32_constant_fold_test_4 377 ; SI-NOT: BFE 378 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 379 ; SI: BUFFER_STORE_DWORD [[VREG]], 380 ; SI: S_ENDPGM 381 ; EG-NOT: BFE 382 define void @bfe_u32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind { 383 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 0, i32 1) nounwind readnone 384 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 385 ret void 386 } 387 388 ; FUNC-LABEL: @bfe_u32_constant_fold_test_5 389 ; SI-NOT: BFE 390 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 391 ; SI: BUFFER_STORE_DWORD [[VREG]], 392 ; SI: S_ENDPGM 393 ; EG-NOT: BFE 394 define void @bfe_u32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind { 395 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 7, i32 1) nounwind readnone 396 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 397 ret void 398 } 399 400 ; FUNC-LABEL: @bfe_u32_constant_fold_test_6 401 ; SI-NOT: BFE 402 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x80 403 ; SI: BUFFER_STORE_DWORD [[VREG]], 404 ; SI: S_ENDPGM 405 ; EG-NOT: BFE 406 define void @bfe_u32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind { 407 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 0, i32 8) nounwind readnone 408 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 409 ret void 410 } 411 412 ; FUNC-LABEL: @bfe_u32_constant_fold_test_7 413 ; SI-NOT: BFE 414 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f 415 ; SI: BUFFER_STORE_DWORD [[VREG]], 416 ; SI: S_ENDPGM 417 ; EG-NOT: BFE 418 define void @bfe_u32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind { 419 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 0, i32 8) nounwind readnone 420 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 421 ret void 422 } 423 424 ; FUNC-LABEL: @bfe_u32_constant_fold_test_8 425 ; SI-NOT: BFE 426 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 427 ; SI: BUFFER_STORE_DWORD [[VREG]], 428 ; SI: S_ENDPGM 429 ; EG-NOT: BFE 430 define void @bfe_u32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind { 431 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 6, i32 8) nounwind readnone 432 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 433 ret void 434 } 435 436 ; FUNC-LABEL: @bfe_u32_constant_fold_test_9 437 ; SI-NOT: BFE 438 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 439 ; SI: BUFFER_STORE_DWORD [[VREG]], 440 ; SI: S_ENDPGM 441 ; EG-NOT: BFEfppppppppppppp 442 define void @bfe_u32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind { 443 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65536, i32 16, i32 8) nounwind readnone 444 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 445 ret void 446 } 447 448 ; FUNC-LABEL: @bfe_u32_constant_fold_test_10 449 ; SI-NOT: BFE 450 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 451 ; SI: BUFFER_STORE_DWORD [[VREG]], 452 ; SI: S_ENDPGM 453 ; EG-NOT: BFE 454 define void @bfe_u32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind { 455 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65535, i32 16, i32 16) nounwind readnone 456 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 457 ret void 458 } 459 460 ; FUNC-LABEL: @bfe_u32_constant_fold_test_11 461 ; SI-NOT: BFE 462 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 10 463 ; SI: BUFFER_STORE_DWORD [[VREG]], 464 ; SI: S_ENDPGM 465 ; EG-NOT: BFE 466 define void @bfe_u32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind { 467 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 4) nounwind readnone 468 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 469 ret void 470 } 471 472 ; FUNC-LABEL: @bfe_u32_constant_fold_test_12 473 ; SI-NOT: BFE 474 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 475 ; SI: BUFFER_STORE_DWORD [[VREG]], 476 ; SI: S_ENDPGM 477 ; EG-NOT: BFE 478 define void @bfe_u32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind { 479 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 31, i32 1) nounwind readnone 480 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 481 ret void 482 } 483 484 ; FUNC-LABEL: @bfe_u32_constant_fold_test_13 485 ; SI-NOT: BFE 486 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 487 ; SI: BUFFER_STORE_DWORD [[VREG]], 488 ; SI: S_ENDPGM 489 ; EG-NOT: BFE 490 define void @bfe_u32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind { 491 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 131070, i32 16, i32 16) nounwind readnone 492 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 493 ret void 494 } 495 496 ; FUNC-LABEL: @bfe_u32_constant_fold_test_14 497 ; SI-NOT: BFE 498 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 40 499 ; SI: BUFFER_STORE_DWORD [[VREG]], 500 ; SI: S_ENDPGM 501 ; EG-NOT: BFE 502 define void @bfe_u32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind { 503 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 2, i32 30) nounwind readnone 504 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 505 ret void 506 } 507 508 ; FUNC-LABEL: @bfe_u32_constant_fold_test_15 509 ; SI-NOT: BFE 510 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 10 511 ; SI: BUFFER_STORE_DWORD [[VREG]], 512 ; SI: S_ENDPGM 513 ; EG-NOT: BFE 514 define void @bfe_u32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind { 515 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 28) nounwind readnone 516 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 517 ret void 518 } 519 520 ; FUNC-LABEL: @bfe_u32_constant_fold_test_16 521 ; SI-NOT: BFE 522 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f 523 ; SI: BUFFER_STORE_DWORD [[VREG]], 524 ; SI: S_ENDPGM 525 ; EG-NOT: BFE 526 define void @bfe_u32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind { 527 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 1, i32 7) nounwind readnone 528 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 529 ret void 530 } 531 532 ; FUNC-LABEL: @bfe_u32_constant_fold_test_17 533 ; SI-NOT: BFE 534 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f 535 ; SI: BUFFER_STORE_DWORD [[VREG]], 536 ; SI: S_ENDPGM 537 ; EG-NOT: BFE 538 define void @bfe_u32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind { 539 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 1, i32 31) nounwind readnone 540 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 541 ret void 542 } 543 544 ; FUNC-LABEL: @bfe_u32_constant_fold_test_18 545 ; SI-NOT: BFE 546 ; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 547 ; SI: BUFFER_STORE_DWORD [[VREG]], 548 ; SI: S_ENDPGM 549 ; EG-NOT: BFE 550 define void @bfe_u32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind { 551 %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 31, i32 1) nounwind readnone 552 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 553 ret void 554 } 555
