1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK --check-prefix=FUNC 2 ;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK --check-prefix=FUNC 3 ;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC 4 5 ;FUNC-LABEL: @test 6 ;EG-CHECK: LOG_IEEE 7 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 8 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 9 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 10 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 11 ;SI-CHECK: V_LOG_F32 12 13 define void @test(float addrspace(1)* %out, float %in) { 14 entry: 15 %0 = call float @llvm.log2.f32(float %in) 16 store float %0, float addrspace(1)* %out 17 ret void 18 } 19 20 ;FUNC-LABEL: @testv2 21 ;EG-CHECK: LOG_IEEE 22 ;EG-CHECK: LOG_IEEE 23 ; FIXME: We should be able to merge these packets together on Cayman so we 24 ; have a maximum of 4 instructions. 25 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 26 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 27 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 28 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 29 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 30 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 31 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 32 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 33 ;SI-CHECK: V_LOG_F32 34 ;SI-CHECK: V_LOG_F32 35 36 define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) { 37 entry: 38 %0 = call <2 x float> @llvm.log2.v2f32(<2 x float> %in) 39 store <2 x float> %0, <2 x float> addrspace(1)* %out 40 ret void 41 } 42 43 ;FUNC-LABEL: @testv4 44 ;EG-CHECK: LOG_IEEE 45 ;EG-CHECK: LOG_IEEE 46 ;EG-CHECK: LOG_IEEE 47 ;EG-CHECK: LOG_IEEE 48 ; FIXME: We should be able to merge these packets together on Cayman so we 49 ; have a maximum of 4 instructions. 50 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 51 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 52 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 53 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 54 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 55 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 56 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 57 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 58 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 59 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 60 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 61 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 62 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 63 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 64 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 65 ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 66 ;SI-CHECK: V_LOG_F32 67 ;SI-CHECK: V_LOG_F32 68 ;SI-CHECK: V_LOG_F32 69 ;SI-CHECK: V_LOG_F32 70 define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) { 71 entry: 72 %0 = call <4 x float> @llvm.log2.v4f32(<4 x float> %in) 73 store <4 x float> %0, <4 x float> addrspace(1)* %out 74 ret void 75 } 76 77 declare float @llvm.log2.f32(float) readnone 78 declare <2 x float> @llvm.log2.v2f32(<2 x float>) readnone 79 declare <4 x float> @llvm.log2.v4f32(<4 x float>) readnone 80
