1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s 2 ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s 3 4 ;EG-CHECK-LABEL: @ashr_v2i32 5 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 6 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 7 8 ;SI-CHECK-LABEL: @ashr_v2i32 9 ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 10 ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 11 12 define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 13 %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 14 %a = load <2 x i32> addrspace(1) * %in 15 %b = load <2 x i32> addrspace(1) * %b_ptr 16 %result = ashr <2 x i32> %a, %b 17 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 18 ret void 19 } 20 21 ;EG-CHECK-LABEL: @ashr_v4i32 22 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 23 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 24 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 25 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 26 27 ;SI-CHECK-LABEL: @ashr_v4i32 28 ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 29 ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 30 ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 31 ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 32 33 define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 34 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 35 %a = load <4 x i32> addrspace(1) * %in 36 %b = load <4 x i32> addrspace(1) * %b_ptr 37 %result = ashr <4 x i32> %a, %b 38 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 39 ret void 40 } 41 42 ;EG-CHECK-LABEL: @ashr_i64 43 ;EG-CHECK: ASHR 44 45 ;SI-CHECK-LABEL: @ashr_i64 46 ;SI-CHECK: S_ASHR_I64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 47 define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) { 48 entry: 49 %0 = sext i32 %in to i64 50 %1 = ashr i64 %0, 8 51 store i64 %1, i64 addrspace(1)* %out 52 ret void 53 } 54 55 ;EG-CHECK-LABEL: @ashr_i64_2 56 ;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] 57 ;EG-CHECK: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} 58 ;EG-CHECK: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 59 ;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 60 ;EG-CHECK-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] 61 ;EG-CHECK-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}} 62 ;EG-CHECK-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}} 63 ;EG-CHECK-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal 64 ;EG-CHECK-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal 65 ;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 66 ;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} 67 ;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} 68 69 ;SI-CHECK-LABEL: @ashr_i64_2 70 ;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 71 define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 72 entry: 73 %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1 74 %a = load i64 addrspace(1) * %in 75 %b = load i64 addrspace(1) * %b_ptr 76 %result = ashr i64 %a, %b 77 store i64 %result, i64 addrspace(1)* %out 78 ret void 79 } 80 81 ;EG-CHECK-LABEL: @ashr_v2i64 82 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 83 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 84 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]] 85 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]] 86 ;EG-CHECK-DAG: LSHL {{.*}}, 1 87 ;EG-CHECK-DAG: LSHL {{.*}}, 1 88 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]] 89 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]] 90 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] 91 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] 92 ;EG-CHECK-DAG: OR_INT 93 ;EG-CHECK-DAG: OR_INT 94 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 95 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 96 ;EG-CHECK-DAG: ASHR 97 ;EG-CHECK-DAG: ASHR 98 ;EG-CHECK-DAG: ASHR {{.*}}, literal 99 ;EG-CHECK-DAG: ASHR {{.*}}, literal 100 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 101 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 102 ;EG-CHECK-DAG: CNDE_INT 103 ;EG-CHECK-DAG: CNDE_INT 104 ;EG-CHECK-DAG: CNDE_INT 105 ;EG-CHECK-DAG: CNDE_INT 106 107 ;SI-CHECK-LABEL: @ashr_v2i64 108 ;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 109 ;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 110 111 define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 112 %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1 113 %a = load <2 x i64> addrspace(1) * %in 114 %b = load <2 x i64> addrspace(1) * %b_ptr 115 %result = ashr <2 x i64> %a, %b 116 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 117 ret void 118 } 119 120 ;EG-CHECK-LABEL: @ashr_v4i64 121 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 122 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 123 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] 124 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] 125 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]] 126 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]] 127 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHC]] 128 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHD]] 129 ;EG-CHECK-DAG: LSHL {{.*}}, 1 130 ;EG-CHECK-DAG: LSHL {{.*}}, 1 131 ;EG-CHECK-DAG: LSHL {{.*}}, 1 132 ;EG-CHECK-DAG: LSHL {{.*}}, 1 133 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]] 134 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]] 135 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHC]] 136 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHD]] 137 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] 138 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] 139 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] 140 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] 141 ;EG-CHECK-DAG: OR_INT 142 ;EG-CHECK-DAG: OR_INT 143 ;EG-CHECK-DAG: OR_INT 144 ;EG-CHECK-DAG: OR_INT 145 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 146 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 147 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal 148 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal 149 ;EG-CHECK-DAG: ASHR 150 ;EG-CHECK-DAG: ASHR 151 ;EG-CHECK-DAG: ASHR 152 ;EG-CHECK-DAG: ASHR 153 ;EG-CHECK-DAG: ASHR {{.*}}, literal 154 ;EG-CHECK-DAG: ASHR {{.*}}, literal 155 ;EG-CHECK-DAG: ASHR {{.*}}, literal 156 ;EG-CHECK-DAG: ASHR {{.*}}, literal 157 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 158 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 159 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal 160 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal 161 ;EG-CHECK-DAG: CNDE_INT 162 ;EG-CHECK-DAG: CNDE_INT 163 ;EG-CHECK-DAG: CNDE_INT 164 ;EG-CHECK-DAG: CNDE_INT 165 ;EG-CHECK-DAG: CNDE_INT 166 ;EG-CHECK-DAG: CNDE_INT 167 ;EG-CHECK-DAG: CNDE_INT 168 ;EG-CHECK-DAG: CNDE_INT 169 170 ;SI-CHECK-LABEL: @ashr_v4i64 171 ;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 172 ;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 173 ;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 174 ;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 175 176 define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 177 %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1 178 %a = load <4 x i64> addrspace(1) * %in 179 %b = load <4 x i64> addrspace(1) * %b_ptr 180 %result = ashr <4 x i64> %a, %b 181 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 182 ret void 183 } 184 185
