Lines Matching defs:pc
121 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker.
127 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker.
673 EmitDataProcessing(AL, TST, 1, PC, R0, ShifterOperand(0));
816 case TST: thumb_opcode = 0U /* 0b0000 */; set_cc = true; rd = PC; break;
817 case TEQ: thumb_opcode = 4U /* 0b0100 */; set_cc = true; rd = PC; break;
818 case CMP: thumb_opcode = 13U /* 0b1101 */; set_cc = true; rd = PC; break;
819 case CMN: thumb_opcode = 8U /* 0b1000 */; set_cc = true; rd = PC; break;
821 case MOV: thumb_opcode = 2U /* 0b0010 */; rn = PC; break;
823 case MVN: thumb_opcode = 3U /* 0b0011 */; rn = PC; break;
1331 offset -= 4; // Account for PC offset.
1374 if (IsHighRegister(rn) && rn != SP && rn != PC) {
1468 if (ad.GetRegister() == PC) {
1469 // PC relative literal encoding.
1532 (regs & 0xff00 & ~(1 << (load ? PC : LR))) == 0) {
1535 ((regs & (1 << (load ? PC : LR))) != 0 ? B8 : 0) | (regs & 0x00ff);
1572 // Cannot have PC or SP in the list.
1573 CHECK_EQ((regs & (1 << PC | 1 << SP)), 0);
1593 uint32_t pc = buffer_.Size();
1610 Branch::Size size = AddBranch(branch_type, pc, label->Position(), cond); // Resolved branch.
1624 uint16_t branch_id = AddBranch(branch_type, pc, cond); // Unresolved branch.
1640 CHECK_NE(rd, PC);
1641 CHECK_NE(rm, PC);
1809 CHECK_NE(rt, PC);
1824 CHECK_NE(rt, PC);
1841 CHECK_NE(rt, PC);
1844 CHECK_NE(rt2, PC);
1862 CHECK_NE(rt, PC);
1865 CHECK_NE(rt2, PC);
1883 CHECK_NE(rt, PC);
1886 CHECK_NE(rt2, PC);
1903 CHECK_NE(rt, PC);
1906 CHECK_NE(rt2, PC);
1934 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC);
1961 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC);
2090 (static_cast<int32_t>(PC)*B12) |
2279 // current pc.
2389 // The offset is off by 4 due to the way the ARM CPUs read PC.
