Lines Matching full:shamt
34 int shamt, int funct) {
42 shamt << kShamtShift |
252 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) {
253 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);
256 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) {
257 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02);
260 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) {
261 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03);
276 void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) {
277 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x38);
280 void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) {
281 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3a);
284 void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) {
285 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3b);
288 void Mips64Assembler::Dsll32(GpuRegister rd, GpuRegister rt, int shamt) {
289 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3c);
292 void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) {
293 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3e);
296 void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) {
297 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3f);
