Lines Matching refs:EmitRex64
110 EmitRex64(dst);
115 EmitRex64(dst);
134 EmitRex64(dst);
143 // 0x89 is movq r/m64 <- r64, with op1 in r/m and op2 in reg: so reverse EmitRex64
144 EmitRex64(src, dst);
160 EmitRex64(dst, src);
176 EmitRex64(src, dst);
338 EmitRex64(dst, src);
393 EmitRex64(dst, src);
401 EmitRex64(dst, src);
655 EmitRex64(dst, src);
670 EmitRex64(dst, src);
690 EmitRex64(dst, src);
705 EmitRex64(dst, src);
765 EmitRex64(dst, src);
785 EmitRex64(dst, src);
1178 EmitRex64(src_rax ? dst : src);
1185 EmitRex64(src, dst);
1247 EmitRex64(reg0, reg1);
1256 EmitRex64(reg);
1263 EmitRex64(reg, address);
1272 EmitRex64(address);
1337 EmitRex64(reg1, reg2);
1345 EmitRex64(reg, address);
1377 EmitRex64(reg);
1384 EmitRex64(dst, src);
1392 EmitRex64(dst, src);
1424 EmitRex64(dst);
1431 EmitRex64(dst, src);
1439 EmitRex64(dst, src);
1470 EmitRex64(dst, src);
1479 EmitRex64(dst);
1485 EmitRex64(dst, src);
1554 EmitRex64(reg);
1561 EmitRex64(dst, address);
1569 // 0x01 is addq r/m64 <- r/m64 + r64, with op1 in r/m and op2 in reg: so reverse EmitRex64
1570 EmitRex64(src, dst);
1609 EmitRex64(reg);
1616 EmitRex64(dst, src);
1624 EmitRex64(reg, address);
1646 EmitRex64();
1661 EmitRex64(reg);
1708 EmitRex64(dst, src);
1723 EmitRex64(dst, reg);
1742 EmitRex64(reg, address);
1759 EmitRex64(reg);
1859 EmitRex64(reg);
1875 EmitRex64(reg);
2007 EmitRex64(reg, address);
2184 EmitRex64(reg);
2206 EmitRex64(operand);
2285 void X86_64Assembler::EmitRex64() {
2289 void X86_64Assembler::EmitRex64(CpuRegister reg) {
2293 void X86_64Assembler::EmitRex64(const Operand& operand) {
2299 void X86_64Assembler::EmitRex64(CpuRegister dst, CpuRegister src) {
2303 void X86_64Assembler::EmitRex64(XmmRegister dst, CpuRegister src) {
2307 void X86_64Assembler::EmitRex64(CpuRegister dst, XmmRegister src) {
2311 void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) {
2319 void X86_64Assembler::EmitRex64(XmmRegister dst, const Operand& operand) {
