Lines Matching full:instruction
27 inline bool Instruction::HasVRegA() const {
57 inline int32_t Instruction::VRegA() const {
84 LOG(FATAL) << "Tried to access vA of instruction " << Name() << " which has no A operand.";
89 inline int8_t Instruction::VRegA_10t(uint16_t inst_data) const {
94 inline uint8_t Instruction::VRegA_10x(uint16_t inst_data) const {
99 inline uint4_t Instruction::VRegA_11n(uint16_t inst_data) const {
104 inline uint8_t Instruction::VRegA_11x(uint16_t inst_data) const {
109 inline uint4_t Instruction::VRegA_12x(uint16_t inst_data) const {
114 inline int16_t Instruction::VRegA_20t() const {
119 inline uint8_t Instruction::VRegA_21c(uint16_t inst_data) const {
124 inline uint8_t Instruction::VRegA_21h(uint16_t inst_data) const {
129 inline uint8_t Instruction::VRegA_21s(uint16_t inst_data) const {
134 inline uint8_t Instruction::VRegA_21t(uint16_t inst_data) const {
139 inline uint8_t Instruction::VRegA_22b(uint16_t inst_data) const {
144 inline uint4_t Instruction::VRegA_22c(uint16_t inst_data) const {
149 inline uint4_t Instruction::VRegA_22s(uint16_t inst_data) const {
154 inline uint4_t Instruction::VRegA_22t(uint16_t inst_data) const {
159 inline uint8_t Instruction::VRegA_22x(uint16_t inst_data) const {
164 inline uint8_t Instruction::VRegA_23x(uint16_t inst_data) const {
169 inline int32_t Instruction::VRegA_30t() const {
174 inline uint8_t Instruction::VRegA_31c(uint16_t inst_data) const {
179 inline uint8_t Instruction::VRegA_31i(uint16_t inst_data) const {
184 inline uint8_t Instruction::VRegA_31t(uint16_t inst_data) const {
189 inline uint16_t Instruction::VRegA_32x() const {
194 inline uint4_t Instruction::VRegA_35c(uint16_t inst_data) const {
199 inline uint8_t Instruction::VRegA_3rc(uint16_t inst_data) const {
204 inline uint8_t Instruction::VRegA_51l(uint16_t inst_data) const {
212 inline bool Instruction::HasVRegB() const {
237 inline bool Instruction::HasWideVRegB() const {
241 inline int32_t Instruction::VRegB() const {
263 LOG(FATAL) << "Tried to access vB of instruction " << Name() << " which has no B operand.";
268 inline uint64_t Instruction::WideVRegB() const {
272 inline int4_t Instruction::VRegB_11n(uint16_t inst_data) const {
277 inline uint4_t Instruction::VRegB_12x(uint16_t inst_data) const {
282 inline uint16_t Instruction::VRegB_21c() const {
287 inline uint16_t Instruction::VRegB_21h() const {
292 inline int16_t Instruction::VRegB_21s() const {
297 inline int16_t Instruction::VRegB_21t() const {
302 inline uint8_t Instruction::VRegB_22b() const {
307 inline uint4_t Instruction::VRegB_22c(uint16_t inst_data) const {
312 inline uint4_t Instruction::VRegB_22s(uint16_t inst_data) const {
317 inline uint4_t Instruction::VRegB_22t(uint16_t inst_data) const {
322 inline uint16_t Instruction::VRegB_22x() const {
327 inline uint8_t Instruction::VRegB_23x() const {
332 inline uint32_t Instruction::VRegB_31c() const {
337 inline int32_t Instruction::VRegB_31i() const {
342 inline int32_t Instruction::VRegB_31t() const {
347 inline uint16_t Instruction::VRegB_32x() const {
352 inline uint16_t Instruction::VRegB_35c() const {
357 inline uint16_t Instruction::VRegB_3rc() const {
362 inline uint64_t Instruction::VRegB_51l() const {
371 inline bool Instruction::HasVRegC() const {
384 inline int32_t Instruction::VRegC() const {
394 LOG(FATAL) << "Tried to access vC of instruction " << Name() << " which has no C operand.";
399 inline int8_t Instruction::VRegC_22b() const {
404 inline uint16_t Instruction::VRegC_22c() const {
409 inline int16_t Instruction::VRegC_22s() const {
414 inline int16_t Instruction::VRegC_22t() const {
419 inline uint8_t Instruction::VRegC_23x() const {
424 inline uint4_t Instruction::VRegC_35c() const {
429 inline uint16_t Instruction::VRegC_3rc() const {
434 inline bool Instruction::HasVarArgs() const {
438 inline void Instruction::GetVarArgs(uint32_t arg[5], uint16_t inst_data) const {
