Lines Matching refs:surf_man
90 typedef int (*hw_init_surface_t)(struct radeon_surface_manager *surf_man,
92 typedef int (*hw_best_surface_t)(struct radeon_surface_manager *surf_man,
132 static int radeon_get_family(struct radeon_surface_manager *surf_man)
134 switch (surf_man->device_id) {
135 #define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break;
195 static int r6_init_hw_info(struct radeon_surface_manager *surf_man)
201 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
207 surf_man->hw_info.allow_2d = 0;
208 version = drmGetVersion(surf_man->fd);
210 surf_man->hw_info.allow_2d = 1;
216 surf_man->hw_info.num_pipes = 1;
219 surf_man->hw_info.num_pipes = 2;
222 surf_man->hw_info.num_pipes = 4;
225 surf_man->hw_info.num_pipes = 8;
228 surf_man->hw_info.num_pipes = 8;
229 surf_man->hw_info.allow_2d = 0;
235 surf_man->hw_info.num_banks = 4;
238 surf_man->hw_info.num_banks = 8;
241 surf_man->hw_info.num_banks = 8;
242 surf_man->hw_info.allow_2d = 0;
248 surf_man->hw_info.group_bytes = 256;
251 surf_man->hw_info.group_bytes = 512;
254 surf_man->hw_info.group_bytes = 256;
255 surf_man->hw_info.allow_2d = 0;
261 static int r6_surface_init_linear(struct radeon_surface_manager *surf_man,
270 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
275 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe);
295 static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man,
304 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
306 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
323 static int r6_surface_init_1d(struct radeon_surface_manager *surf_man,
332 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
340 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
356 static int r6_surface_init_2d(struct radeon_surface_manager *surf_man,
366 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) /
368 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign);
371 yalign = tilew * surf_man->hw_info.num_pipes;
377 MAX2(surf_man->hw_info.num_pipes *
378 surf_man->hw_info.num_banks *
388 return r6_surface_init_1d(surf_man, surf, offset, i);
399 static int r6_surface_init(struct radeon_surface_manager *surf_man,
429 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
452 r = r6_surface_init_linear(surf_man, surf, 0, 0);
455 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
458 r = r6_surface_init_1d(surf_man, surf, 0, 0);
461 r = r6_surface_init_2d(surf_man, surf, 0, 0);
469 static int r6_surface_best(struct radeon_surface_manager *surf_man,
480 static int eg_init_hw_info(struct radeon_surface_manager *surf_man)
486 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
492 surf_man->hw_info.allow_2d = 0;
493 version = drmGetVersion(surf_man->fd);
495 surf_man->hw_info.allow_2d = 1;
501 surf_man->hw_info.num_pipes = 1;
504 surf_man->hw_info.num_pipes = 2;
507 surf_man->hw_info.num_pipes = 4;
510 surf_man->hw_info.num_pipes = 8;
513 surf_man->hw_info.num_pipes = 8;
514 surf_man->hw_info.allow_2d = 0;
520 surf_man->hw_info.num_banks = 4;
523 surf_man->hw_info.num_banks = 8;
526 surf_man->hw_info.num_banks = 16;
529 surf_man->hw_info.num_banks = 8;
530 surf_man->hw_info.allow_2d = 0;
536 surf_man->hw_info.group_bytes = 256;
539 surf_man->hw_info.group_bytes = 512;
542 surf_man->hw_info.group_bytes = 256;
543 surf_man->hw_info.allow_2d = 0;
549 surf_man->hw_info.row_size = 1024;
552 surf_man->hw_info.row_size = 2048;
555 surf_man->hw_info.row_size = 4096;
558 surf_man->hw_info.row_size = 4096;
559 surf_man->hw_info.allow_2d = 0;
606 static int eg_surface_init_1d(struct radeon_surface_manager *surf_man,
617 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples);
626 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes);
647 static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
670 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
671 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
689 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i);
700 static int eg_surface_sanity(struct radeon_surface_manager *surf_man,
717 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
751 if (surf_man->hw_info.num_banks < surf->mtilea) {
775 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
783 static int eg_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man,
793 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0);
798 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1,
805 static int eg_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man,
815 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe,
821 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1,
828 static int eg_surface_init(struct radeon_surface_manager *surf_man,
857 r = eg_surface_sanity(surf_man, surf, mode);
868 r = r6_surface_init_linear(surf_man, surf, 0, 0);
871 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
874 r = eg_surface_init_1d_miptrees(surf_man, surf);
877 r = eg_surface_init_2d_miptrees(surf_man, surf);
903 static int eg_surface_best(struct radeon_surface_manager *surf_man,
916 surf->mtilea = surf_man->hw_info.num_banks;
919 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
927 r = eg_surface_sanity(surf_man, surf, mode);
967 surf->tile_split = surf_man->hw_info.row_size;
968 surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
1006 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
1011 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) /
1012 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16;
1192 static int si_init_hw_info(struct radeon_surface_manager *surf_man)
1198 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
1204 surf_man->hw_info.allow_2d = 0;
1205 version = drmGetVersion(surf_man->fd);
1207 if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_array)) {
1208 surf_man->hw_info.allow_2d = 1;
1215 surf_man->hw_info.num_pipes = 1;
1218 surf_man->hw_info.num_pipes = 2;
1221 surf_man->hw_info.num_pipes = 4;
1224 surf_man->hw_info.num_pipes = 8;
1227 surf_man->hw_info.num_pipes = 8;
1228 surf_man->hw_info.allow_2d = 0;
1234 surf_man->hw_info.num_banks = 4;
1237 surf_man->hw_info.num_banks = 8;
1240 surf_man->hw_info.num_banks = 16;
1243 surf_man->hw_info.num_banks = 8;
1244 surf_man->hw_info.allow_2d = 0;
1250 surf_man->hw_info.group_bytes = 256;
1253 surf_man->hw_info.group_bytes = 512;
1256 surf_man->hw_info.group_bytes = 256;
1257 surf_man->hw_info.allow_2d = 0;
1263 surf_man->hw_info.row_size = 1024;
1266 surf_man->hw_info.row_size = 2048;
1269 surf_man->hw_info.row_size = 4096;
1272 surf_man->hw_info.row_size = 4096;
1273 surf_man->hw_info.allow_2d = 0;
1279 static int si_surface_sanity(struct radeon_surface_manager *surf_man,
1297 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) {
1340 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode];
1391 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode];
1509 static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_man,
1519 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
1524 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes);
1542 static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
1549 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes);
1556 slice_align = surf_man->hw_info.group_bytes;
1591 static int si_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man,
1597 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0);
1603 r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0);
1609 static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
1673 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
1693 static int si_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man,
1702 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1705 r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, surf->tile_split, 0, 0);
1711 r = si_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_banks, surf->stencil_tile_split, surf->bo_size, 0);
1717 static int si_surface_init(struct radeon_surface_manager *surf_man,
1746 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1757 r = r6_surface_init_linear(surf_man, surf, 0, 0);
1760 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
1763 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1766 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1777 static int si_surface_best(struct radeon_surface_manager *surf_man,
1792 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1849 static void cik_get_2d_params(struct radeon_surface_manager *surf_man,
1859 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1937 tile_split = MIN2(surf_man->hw_info.row_size, tile_split);
1945 gb_macrotile_mode = surf_man->hw_info.macrotile_mode_array[macrotile_index];
2020 static int cik_init_hw_info(struct radeon_surface_manager *surf_man)
2026 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
2032 surf_man->hw_info.allow_2d = 0;
2033 version = drmGetVersion(surf_man->fd);
2035 if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_array) &&
2036 !radeon_get_value(surf_man->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, surf_man->hw_info.macrotile_mode_array)) {
2037 surf_man->hw_info.allow_2d = 1;
2044 surf_man->hw_info.num_pipes = 1;
2047 surf_man->hw_info.num_pipes = 2;
2050 surf_man->hw_info.num_pipes = 4;
2053 surf_man->hw_info.num_pipes = 8;
2056 surf_man->hw_info.num_pipes = 8;
2057 surf_man->hw_info.allow_2d = 0;
2063 surf_man->hw_info.num_banks = 4;
2066 surf_man->hw_info.num_banks = 8;
2069 surf_man->hw_info.num_banks = 16;
2072 surf_man->hw_info.num_banks = 8;
2073 surf_man->hw_info.allow_2d = 0;
2079 surf_man->hw_info.group_bytes = 256;
2082 surf_man->hw_info.group_bytes = 512;
2085 surf_man->hw_info.group_bytes = 256;
2086 surf_man->hw_info.allow_2d = 0;
2092 surf_man->hw_info.row_size = 1024;
2095 surf_man->hw_info.row_size = 2048;
2098 surf_man->hw_info.row_size = 4096;
2101 surf_man->hw_info.row_size = 4096;
2102 surf_man->hw_info.allow_2d = 0;
2108 static int cik_surface_sanity(struct radeon_surface_manager *surf_man,
2124 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) {
2168 cik_get_2d_params(surf_man, 1, surf->nsamples, false,
2180 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples,
2206 static int cik_surface_init_2d(struct radeon_surface_manager *surf_man,
2226 tile_split = MIN2(surf_man->hw_info.row_size, tile_split);
2275 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
2295 static int cik_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man,
2302 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples,
2306 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode,
2313 r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode,
2321 static int cik_surface_init(struct radeon_surface_manager *surf_man,
2350 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2361 r = r6_surface_init_linear(surf_man, surf, 0, 0);
2364 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
2367 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2370 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2381 static int cik_surface_best(struct radeon_surface_manager *surf_man,
2396 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2406 struct radeon_surface_manager *surf_man;
2408 surf_man = calloc(1, sizeof(struct radeon_surface_manager));
2409 if (surf_man == NULL) {
2412 surf_man->fd = fd;
2413 if (radeon_get_value(fd, RADEON_INFO_DEVICE_ID, &surf_man->device_id)) {
2416 if (radeon_get_family(surf_man)) {
2420 if (surf_man->family <= CHIP_RV740) {
2421 if (r6_init_hw_info(surf_man)) {
2424 surf_man->surface_init = &r6_surface_init;
2425 surf_man->surface_best = &r6_surface_best;
2426 } else if (surf_man->family <= CHIP_ARUBA) {
2427 if (eg_init_hw_info(surf_man)) {
2430 surf_man->surface_init = &eg_surface_init;
2431 surf_man->surface_best = &eg_surface_best;
2432 } else if (surf_man->family < CHIP_BONAIRE) {
2433 if (si_init_hw_info(surf_man)) {
2436 surf_man->surface_init = &si_surface_init;
2437 surf_man->surface_best = &si_surface_best;
2439 if (cik_init_hw_info(surf_man)) {
2442 surf_man->surface_init = &cik_surface_init;
2443 surf_man->surface_best = &cik_surface_best;
2446 return surf_man;
2448 free(surf_man);
2453 radeon_surface_manager_free(struct radeon_surface_manager *surf_man)
2455 free(surf_man);
2458 static int radeon_surface_sanity(struct radeon_surface_manager *surf_man,
2463 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) {
2505 if (surf_man->family >= CHIP_RV770) {
2526 radeon_surface_init(struct radeon_surface_manager *surf_man,
2535 r = radeon_surface_sanity(surf_man, surf, type, mode);
2539 return surf_man->surface_init(surf_man, surf);
2543 radeon_surface_best(struct radeon_surface_manager *surf_man,
2552 r = radeon_surface_sanity(surf_man, surf, type, mode);
2556 return surf_man->surface_best(surf_man, surf);
