Lines Matching defs:imm5
3191 uint32_t imm5; // encoding for the shift amount
3214 imm5 = Bits32(opcode, 10, 6);
3225 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6);
3233 imm5 = Bits32(opcode, 11, 7);
3240 if (shift_type == SRType_ROR && imm5 == 0)
3249 uint32_t amt = (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5));
3888 imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32);
4596 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
4817 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
4819 uint32_t imm5 = Bits32 (opcode, 11, 7);
4820 shift_n = DecodeImmShift(typ, imm5, shift_t);
4942 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
6013 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
6015 uint32_t imm5 = Bits32 (opcode, 11, 7);
6016 shift_n = DecodeImmShift (type, imm5, shift_t);
6156 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
6425 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
6427 uint32_t imm5 = Bits32 (opcode, 11, 7);
6428 shift_n = DecodeImmShift (type, imm5, shift_t);
6534 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32);
9486 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
9699 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
12141 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
12737 { 0xfffff800, 0x00007800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>{,#<imm5>}]" },
12780 { 0xfffff800, 0x00007000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt>, [<Rn>, #<imm5>]" },
