Lines Matching defs:pc
439 const uint32_t pc = ReadCoreReg(PC_REG, &success);
442 if (!MemAWrite (context, addr, pc, addr_byte_size))
494 // The P bit represents PC.
773 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
870 // if Rd == ?1111? && S == ?1? then SEE SUBS PC, LR and related instructions;
1078 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1179 // PC relative immediate load into register, possibly followed by ADD (SP plus register).
1189 base = Align(PC,4);
1207 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1211 // PC relative immediate load context
1219 uint32_t imm32; // immediate offset from the PC
1222 addr_t address; // the PC relative address
1223 uint32_t data; // the literal data value from the PC relative load
1241 base = Align(pc, 4);
1420 // at a PC-relative address, and changes instruction set from ARM to Thumb, or
1432 LR = PC - 4;
1434 LR = PC<31:1> : '1';
1436 targetAddress = Align(PC,4) + imm32;
1438 targetAddress = PC + imm32;
1450 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1455 int32_t imm32; // PC-relative offset
1459 lr = pc | 1u; // return address
1469 target = pc + imm32;
1477 lr = pc | 1u; // return address
1487 target = Align(pc, 4) + imm32;
1494 lr = pc - 4; // return address
1496 target = Align(pc, 4) + imm32;
1500 lr = pc - 4; // return address
1502 target = pc + imm32;
1529 next_instr_addr = PC - 4;
1532 next_instr_addr = PC - 2;
1544 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1551 lr = (pc - 2) | 1u; // return address
1560 lr = pc - 4; // return address
1851 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1963 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1966 if (!MemUWrite (context, addr, pc, addr_byte_size))
2192 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2200 lr = (pc + 2) | 1u; // return address
2205 lr = pc + 4; // return address
2252 BranchWritePC(PC + imm32);
2262 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2266 int32_t imm32; // PC-relative offset
2271 target = pc + imm32;
2276 target = pc + imm32;
2289 target = pc + imm32;
2304 target = pc + imm32;
2310 target = pc + imm32;
2332 BranchWritePC(PC + imm32);
2344 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2349 uint32_t imm32; // PC-relative offset to branch forward
2355 target = pc + imm32;
2368 // Table Branch Byte causes a PC-relative forward branch using a table of single byte offsets.
2372 // Table Branch Halfword causes a PC-relative forward branch using a table of single halfword offsets.
2386 BranchWritePC(PC + 2*halfwords);
2409 // The PC can be used, in which case the table immediately follows this instruction.
2422 // PC-relative offset to branch forward
2429 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2434 addr_t target = pc + offset;
4139 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4143 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4264 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4268 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4415 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4419 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4541 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4545 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
5386 // This instruction adds an immediate value to the PC value to form a PC-relative address,
5395 result = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32);
5407 uint32_t imm32; // the immediate value to be added/subtracted to/from the PC
5434 // Read the PC value.
5435 uint32_t pc = ReadCoreReg(PC_REG, &success);
5439 uint32_t result = (add ? Align(pc, 4) + imm32 : Align(pc, 4) - imm32);
5661 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5743 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
6263 // LDRB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory,
6271 base = Align(PC,4);
6313 // base = Align(PC,4);
6649 // LDRH (literal) caculates an address from the PC value and an immediate offset, loads a halfword from memory,
6657 base = Align(PC,4);
6710 // base = Align(PC,4);
7081 // LDRSB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory,
7089 base = Align(PC,4);
7138 // base = Align(PC,4);
7489 // LDRSH (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory,
7497 base = Align(PC,4);
7549 // base = Align(PC,4);
8102 // RFE (Return From Exception) loads the PC and the CPSR from the word at the specified address and the following
8298 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8383 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8629 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8701 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8767 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8830 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8904 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8983 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
9147 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
9482 // if Rd == ?1111? && S == ?1? then SEE SUBS PC, LR and related instructions;
9695 // if Rd == ?1111? && S == ?1? then SEE SUBS PC, LR and related instructions;
11016 base = if n == 15 then Align(PC,4) else R[n];
11074 // base = if n == 15 then Align(PC,4) else R[n];
12069 // B6.2.13 SUBS PC, LR and related instructions
12070 //The SUBS PC, LR, #<const? instruction provides an exception return without the use of the stack. It subtracts the
12334 { 0x0fff0000, 0x028f0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12335 { 0x0fff0000, 0x024f0000, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12417 // subs pc, lr and related instructions
12418 { 0x0e10f000, 0x0210f000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,#<const> | <Rn>,#<const>" },
12419 { 0x0e10f010, 0x0010f000, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,<Rn>,<Rm{,<shift>}" },
12516 // PC-relative load into register (see also EmulateADDSPRm)
12517 { 0xfffff800, 0x00004800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"},
12595 { 0xfffff800, 0x0000a000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12596 { 0xfbff8000, 0xf2af0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12597 { 0xfbff8000, 0xf20f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12712 // subs pc, lr and related instructions
12713 { 0xffffff00, 0xf3de8f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "SUBS<c> PC, LR, #<imm8>" },
12733 // Thumb2 PC-relative load into register
12734 { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"},
12876 addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success);
12886 uint32_t thumb_opcode = MemARead(read_inst_context, pc, 2, 0, &success);
12896 m_opcode.SetOpcode32 ((thumb_opcode << 16) | MemARead(read_inst_context, pc + 2, 2, 0, &success));
12903 m_opcode.SetOpcode32 (MemARead(read_inst_context, pc, 4, 0, &success));
13315 // When executing an ARM instruction , PC reads as the address of the current
13317 // When executing a Thumb instruction , PC reads as the address of the current
13589 // case LLDB_REGNUM_GENERIC_PC: return "pc";
13615 // Our previous PC is in the LR
