Lines Matching refs:then
374 // if BitCount(registers) < 1 then UNPREDICTABLE;
381 // if BitCount(registers) < 2 then UNPREDICTABLE;
387 // if BadReg(t) then UNPREDICTABLE;
396 // if BitCount(register_list) < 2 then SEE STMDB / STMFD;
400 // if t == 13 then UNPREDICTABLE;
468 if registers<i> == '1' then
469 R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4;
470 if registers<15> == '1' then
471 if UnalignedAllowed then
475 if registers<13> == '0' then SP = SP + 4*BitCount(registers);
476 if registers<13> == '1' then SP = bits(32) UNKNOWN;
497 // if BitCount(registers) < 1 then UNPREDICTABLE;
504 // if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
507 // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
513 // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE;
524 // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD;
526 // if registers<13> == '1' && ArchVersion() >= 7 then UNPREDICTABLE;
532 // if t == 13 then UNPREDICTABLE;
599 if d == 15 then
603 if setflags then
658 if d == 15 then
662 if setflags then
723 if d == 15 then
727 if setflags then
761 // if setflags && (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
764 // if !setflags && (d == 15 || m == 15 || (d == 13 && m == 13)) then UNPREDICTABLE;
773 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
809 if d == 15 then // Can only occur for ARM encoding
813 if setflags then
858 // if BadReg(d) then UNPREDICTABLE;
870 // if Rd == ?1111? && S == ?1? then SEE SUBS PC, LR and related instructions;
885 // if d == 15 then UNPREDICTABLE;
917 if ConditionPassed() then
923 if setflags then
926 if ArchVersion() == 4 then
949 // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
962 // if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE;
975 // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
979 // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
1017 // if setflags then
1031 // if ArchVersion() == 4 then
1049 if d == 15 then // Can only occur for ARM encoding
1053 if setflags then
1078 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1110 if d == 15 then // Can only occur for ARM encoding
1114 if setflags then
1145 // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
1190 address = if add then (base + imm32) else (base - imm32);
1192 if t == 15 then
1193 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
1194 elsif UnalignedSupport() || address<1:0> = '00' then
1197 if CurrentInstrSet() == InstrSet_ARM then
1286 if d == 15 then // Can only occur for ARM encoding
1290 if setflags then
1371 if d == 15 then
1375 if setflags then
1431 if CurrentInstrSet() == InstrSet_ARM then
1435 if targetInstrSet == InstrSet_ARM then
1528 if CurrentInstrSet() == InstrSet_ARM then
1553 // if m == 15 then UNPREDICTABLE;
1562 // if m == 15 then UNPREDICTABLE;
1640 if JMCR.JE == '0' || CurrentInstrSet() == InstrSet_ThumbEE then
1643 if JazelleAcceptsExecution() then
1696 if d == 15 then // Can only occur for ARM encoding
1700 if setflags then
1748 if d == 15 then // Can only occur for ARM encoding
1752 if setflags then
1802 if d == 15 then // Can only occur for ARM encoding
1806 if setflags then
1851 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1889 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
1890 address = if index then offset_addr else R[n];
1891 MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
1892 if wback then R[n] = offset_addr;
1994 if single_regs then
2000 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
2001 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
2026 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2036 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2091 if single_regs then
2098 D[d+r] = if BigEndian() then word1:word2 else word2:word1;
2122 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2132 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2222 // If Then makes up to four following instructions (the IT block) conditional.
2331 if nonzero ^ IsZero(R[n]) then
2382 if is_tbh then
2450 if ConditionPassed() then
2454 if setflags then
2493 // if Rd == '1111' && S == '1' then SEE CMN (immediate);
2494 // if Rn == '1101' then SEE ADD (SP plus immediate);
2501 // if BadReg(d) || n == 15 then UNPREDICTABLE;
2509 // if Rn == '1111' then SEE ADR;
2510 // if Rn == '1101' then SEE ADD (SP plus immediate);
2520 // if BadReg(d) then UNPREDICTABLE;
2545 //if setflags then
2564 if ConditionPassed() then
2567 if d == 15 then
2571 if setflags then
2623 if ConditionPassed() then
2627 if d == 15 then
2631 if setflags then
2714 if ConditionPassed() then
2764 if ConditionPassed() then
2791 // if n == 15 || BadReg(m) then UNPREDICTABLE;
2834 if ConditionPassed() then
2888 if ConditionPassed() then
2961 if ConditionPassed() then
2964 if d == 15 then // Can only occur for ARM encoding
2968 if setflags then
2987 if ConditionPassed() then
2992 if setflags then
3010 if ConditionPassed() then
3013 if d == 15 then // Can only occur for ARM encoding
3017 if setflags then
3036 if ConditionPassed() then
3041 if setflags then
3059 if ConditionPassed() then
3062 if d == 15 then // Can only occur for ARM encoding
3066 if setflags then
3085 if ConditionPassed() then
3090 if setflags then
3108 if ConditionPassed() then
3111 if d == 15 then // Can only occur for ARM encoding
3115 if setflags then
3134 if ConditionPassed() then
3139 if setflags then
3159 if ConditionPassed() then
3162 if d == 15 then // Can only occur for ARM encoding
3166 if setflags then
3350 if registers<i> == '1' then
3352 if registers<15> == '1' then
3355 if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers);
3356 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3376 // if BitCount(registers) < 1 then UNPREDICTABLE;
3381 // if W == '1' && Rn == '1101' then SEE POP;
3388 // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
3394 // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
3398 // if wback && registers<n> == '1' then UNPREDICTABLE;
3491 if ConditionPassed() then
3496 if registers<i> == '1' then
3499 if registers<15> == '1' then
3502 if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3503 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
3524 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
3552 // if registers<i> == '1' then
3566 // if registers<15> == '1' then
3579 // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3593 // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
3608 if ConditionPassed() then
3613 if registers<i> == '1' then
3615 if registers<15> == '1' then
3618 if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3619 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3639 // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
3645 // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
3649 // if wback && registers<n> == '1' then UNPREDICTABLE;
3661 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
3703 // if registers<15> == '1' then
3716 // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3730 // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3744 if ConditionPassed() then
3749 if registers<i> == '1' then
3751 if registers<15> == '1' then
3754 if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
3755 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
3774 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
3816 // if registers<15> == '1' then
3829 // if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
3843 // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3861 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
3862 address = if index then offset_addr else R[n];
3864 if wback then R[n] = offset_addr;
3865 if t == 15 then
3866 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
3867 elsif UnalignedSupport() || address<1:0> = '00' then
3910 // if Rn == '1111' then SEE LDR (literal);
3921 // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
3928 // if Rn == '1111' then SEE LDR (literal);
3929 // if P == '1' && U == '1' && W == '0' then SEE LDRT;
3930 // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 == '00000100' then SEE POP;
3931 // if P == '0' && W == '0' then UNDEFINED;
3945 // if (wback && n == t) || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE;
4014 if ConditionPassed() then
4019 if registers<i> == '1' then
4020 if i == n && wback && i != LowestSetBit(registers) then
4026 if registers<15> == '1' then // Only possible for encoding A1
4028 if wback then R[n] = R[n] + 4*BitCount(registers);
4050 // if BitCount(registers) < 1 then UNPREDICTABLE;
4063 // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4067 // if wback && registers<n> == '1' then UNPREDICTABLE;
4079 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4104 // if registers<i> == '1' then
4109 // if i == n && wback && i != LowestSetBit(registers) then
4132 // if registers<15> == '1' then // Only possible for encoding A1
4147 // if wback then R[n] = R[n] + 4*BitCount(registers);
4168 if ConditionPassed() then
4173 if registers<i> == '1' then
4174 if i == n && wback && i != LowestSetBit(registers) then
4180 if registers<15> == '1' then
4183 if wback then R[n] = R[n] - 4*BitCount(registers);
4204 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4229 then
4234 //if i == n && wback && i != LowestSetBit(registers) then
4257 // if registers<15> == '1' then
4272 // if wback then R[n] = R[n] - 4*BitCount(registers);
4293 if ConditionPassed() then
4298 if registers<i> == '1' then
4299 if i == n && wback && i != LowestSetBit(registers) then
4305 if registers<15> == '1' then // Only possible for encoding A1
4308 if wback then R[n] = R[n] - 4*BitCount(registers);
4325 // if W == '1' && Rn == '1101' then SEE PUSH;
4335 // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4338 // if wback && registers<n> == '1' then UNPREDICTABLE;
4344 // if W == '1' && Rn == '1101? && BitCount(register_list) >= 2 then SEE PUSH;
4353 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4380 // if registers<i> == '1' then
4385 // if i == n && wback && i != LowestSetBit(registers) then
4408 // if registers<15> == '1' then // Only possible for encoding A1
4423 // if wback then R[n] = R[n] - 4*BitCount(registers);
4444 if ConditionPassed() then
4449 if registers<i> == '1' then
4450 if i == n && wback && i != LowestSetBit(registers) then
4456 if registers<15> == '1' then
4459 if wback then R[n] = R[n] + 4*BitCount(registers);
4480 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4505 // if registers<i> == '1' then
4510 // if i == n && wback && i != LowestSetBit(registers) then
4534 // if registers<15> == '1' then
4549 // if wback then R[n] = R[n] + 4*BitCount(registers);
4569 if ConditionPassed() then
4571 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4572 address = if index then offset_addr else R[n];
4573 if UnalignedSupport() || address<1:0> == '00' then
4577 if wback then R[n] = offset_addr;
4620 // if Rn == '1111' then UNDEFINED;
4634 // if t == 15 then UNPREDICTABLE;
4640 // if P == '1' && U == '1' && W == '0' then SEE STRT;
4641 then SEE PUSH;
4642 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
4657 // if t == 15 || (wback && n == t) then UNPREDICTABLE;
4669 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4679 // address = if index then offset_addr else R[n];
4690 // if UnalignedSupport() || address<1:0> == '00' then
4711 // if wback then R[n] = offset_addr;
4729 if ConditionPassed() then
4732 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
4733 address = if index then offset_addr else R[n];
4734 if t == 15 then // Only possible for encoding A1
4738 if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
4742 if wback then R[n] = offset_addr;
4764 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
4781 // if Rn == '1111' then UNDEFINED;
4799 // if t == 15 || BadReg(m) then UNPREDICTABLE;
4806 // if P == '0' && W == '1' then SEE STRT;
4822 // if m == 15 then UNPREDICTABLE;
4826 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
4853 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
4859 // address = if index then offset_addr else R[n];
4866 // if t == 15 then // Only possible for encoding A1
4880 // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
4902 // if wback then R[n] = offset_addr;
4919 if ConditionPassed() then
4921 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4922 address = if index then offset_addr else R[n];
4924 if wback then R[n] = offset_addr;
4954 // if Rn == '1111' then UNDEFINED;
4968 // if BadReg(t) then UNPREDICTABLE;
4974 // if P == '1' && U == '1' && W == '0' then SEE STRBT;
4975 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
4989 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE
5004 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5010 // address = if index then offset_addr else R[n];
5036 // if wback then R[n] = offset_addr;
5056 if ConditionPassed() then
5059 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5060 address = if index then offset_addr else R[n];
5061 if UnalignedSupport() || address<0> == '0' then
5065 if wback then R[n] = offset_addr;
5085 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
5103 // if Rn == '1111' then UNDEFINED;
5120 // if BadReg(t) || BadReg(m) then UNPREDICTABLE;
5127 // if P == '0' && W == '1' then SEE STRHT;
5142 // if t == 15 || m == 15 then UNPREDICTABLE;
5146 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
5169 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5176 // address = if index then offset_addr else R[n];
5190 // if UnalignedSupport() || address<0> == '0' then
5216 // if wback then R[n] = offset_addr;
5237 if ConditionPassed() then
5240 if d == 15 then // Can only occur for ARM encoding
5244 if setflags then
5306 if ConditionPassed() then
5310 if d == 15 then // Can only occur for ARM encoding
5314 if setflags then
5393 if ConditionPassed() then
5395 result = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32);
5396 if d == 15 then // Can only occur for ARM encodings
5458 if ConditionPassed() then
5461 if d == 15 then // Can only occur for ARM encoding
5465 if setflags then
5487 // if Rd == '1111' && S == '1' then SEE TST (immediate);
5531 if ConditionPassed() then
5535 if d == 15 then // Can only occur for ARM encoding
5539 if setflags then
5570 // if Rd == '1111' && S == '1' then SEE TST (register);
5623 if ConditionPassed() then
5626 if d == 15 then // Can only occur for ARM encoding
5630 if setflags then
5661 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5694 if ConditionPassed() then
5698 if d == 15 then // Can only occur for ARM encoding
5702 if setflags then
5743 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5782 if ConditionPassed() then
5784 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5785 address = if index then offset_addr else R[n];
5787 if wback then R[n] = offset_addr;
5788 if t == 15 then
5789 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5790 elsif UnalignedSupport() || address<1:0> = '00' then
5812 // if Rn == '1111' then SEE LDR (literal);
5813 // if P == '0' && W == '1' then SEE LDRT;
5814 // if Rn == '1101' && P == '0' && U == '1' && W == '0' && imm12 == '000000000100' then SEE POP;
5825 // if wback && n == t then UNPREDICTABLE;
5841 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5847 // address = if index then offset_addr else R[n];
5866 // if wback then R[n] = offset_addr;
5875 // if t == 15 then
5878 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5889 // elsif UnalignedSupport() || address<1:0> = '00' then
5921 if ConditionPassed() then
5924 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5925 address = if index then offset_addr else R[n];
5927 if wback then R[n] = offset_addr;
5928 if t == 15 then
5929 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5930 elsif UnalignedSupport() || address<1:0> = '00' then
5933 if CurrentInstrSet() == InstrSet_ARM then
5957 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
5975 // if Rn == '1111' then SEE LDR (literal);
5990 // if BadReg(m) then UNPREDICTABLE;
5994 // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
6002 // if P == '0' && W == '1' then SEE LDRT;
6018 // if m == 15 then UNPREDICTABLE;
6022 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
6049 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6055 // address = if index then offset_addr else R[n];
6073 // if wback then R[n] = offset_addr;
6082 // if t == 15 then
6085 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
6095 // elsif UnalignedSupport() || address<1:0> = '00' then
6106 // if CurrentInstrSet() == InstrSet_ARM then
6133 if ConditionPassed() then
6135 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6136 address = if index then offset_addr else R[n];
6138 if wback then R[n] = offset_addr;
6169 // if Rt == '1111' then SEE PLD;
6170 // if Rn == '1111' then SEE LDRB (literal);
6181 // if t == 13 then UNPREDICTABLE;
6188 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD;
6189 // if Rn == '1111' then SEE LDRB (literal);
6190 // if P == '1' && U == '1' && W == '0' then SEE LDRBT;
6191 // if P == '0' && W == '0' then UNDEFINED;
6205 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
6222 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6228 // address = if index then offset_addr else R[n];
6251 // if wback then R[n] = offset_addr;
6269 if ConditionPassed() then
6272 address = if add then (base + imm32) else (base - imm32);
6286 // if Rt == '1111' then SEE PLD;
6292 // if t == 13 then UNPREDICTABLE;
6304 // if t == 15 then UNPREDICTABLE;
6321 // address = if add then (base + imm32) else (base - imm32);
6349 if ConditionPassed() then
6352 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6353 address = if index then offset_addr else R[n];
6355 if wback then R[n] = offset_addr;
6391 // if Rt == '1111' then SEE PLD;
6392 // if Rn == '1111' then SEE LDRB (literal);
6407 // if t == 13 || BadReg(m) then UNPREDICTABLE;
6414 // if P == '0' && W == '1' then SEE LDRBT;
6430 // if t == 15 || m == 15 then UNPREDICTABLE;
6434 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
6456 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6466 // address = if index then
6487 // if wback then R[n] = offset_addr;
6506 if ConditionPassed() then
6508 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6509 address = if index then offset_addr else R[n];
6511 if wback then R[n] = offset_addr;
6512 if UnalignedSupport() || address<0> = '0' then
6547 // if Rt == '1111' then SEE "Unallocated memory hints";
6548 // if Rn == '1111' then SEE LDRH (literal);
6559 // if t == 13 then UNPREDICTABLE;
6565 // if Rn == '1111' then SEE LDRH (literal);
6566 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints";
6567 // if P == '1' && U == '1' && W == '0' then SEE LDRHT;
6568 // if P == '0' && W == '0' then UNDEFINED;
6582 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
6591 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6604 // address = if index then offset_addr else R[n];
6622 // if wback then R[n] = offset_addr;
6631 // if UnalignedSupport() || address<0> = '0' then
6655 if ConditionPassed() then
6658 address = if add then (base + imm32) else (base - imm32);
6660 if UnalignedSupport() || address<0> = '0' then
6678 // if Rt == '1111' then SEE "Unallocated memory hints";
6684 // if t == 13 then UNPREDICTABLE;
6700 // if t == 15 then UNPREDICTABLE;
6718 // address = if add then (base + imm32) else (base - imm32);
6737 // if UnalignedSupport() || address<0> = '0' then
6763 if ConditionPassed() then
6766 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6767 address = if index then offset_addr else R[n];
6769 if wback then R[n] = offset_addr;
6770 if UnalignedSupport() || address<0> = '0' then
6793 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
6811 // if Rn == '1111' then SEE LDRH (literal);
6812 // if Rt == '1111' then SEE "Unallocated memory hints";
6827 // if t == 13 || BadReg(m) then UNPREDICTABLE;
6833 // if P == '0' && W == '1' then SEE LDRHT;
6848 // if t == 15 || m == 15 then UNPREDICTABLE;
6852 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
6875 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6885 // address = if index then offset_addr else R[n];
6904 // if wback then R[n] = offset_addr;
6913 // if UnalignedSupport() || address<0> = '0' then
6938 if ConditionPassed() then
6940 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6941 address = if index then offset_addr else R[n];
6943 if wback then R[n] = offset_addr;
6961 // if Rt == '1111' then SEE PLI;
6962 // if Rn == '1111' then SEE LDRSB (literal);
6973 // if t == 13 then UNPREDICTABLE;
6980 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLI;
6981 // if Rn == '1111' then SEE LDRSB (literal);
6982 // if P == '1' && U == '1' && W == '0' then SEE LDRSBT;
6983 // if P == '0' && W == '0' then UNDEFINED;
6997 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
7007 // if Rn == '1111' then SEE LDRSB (literal);
7008 // if P == '0' && W == '1' then SEE LDRSBT;
7022 // if t == 15 || (wback && n == t) then UNPREDICTABLE;
7040 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
7046 // address = if index then offset_addr else R[n];
7068 // if wback then R[n] = offset_addr;
7087 if ConditionPassed() then
7090 address = if add then (base + imm32) else (base - imm32);
7106 // if Rt == '1111' then SEE PLI;
7112 // if t == 13 then UNPREDICTABLE;
7127 // if t == 15 then UNPREDICTABLE;
7144 // address = if add then (base + imm32) else (base - imm32);
7177 if ConditionPassed() then
7180 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7181 address = if index then offset_addr else R[n];
7183 if wback then R[n] = offset_addr;
7220 // if Rt == '1111' then SEE PLI;
7221 // if Rn == '1111' then SEE LDRSB (literal);
7236 // if t == 13 || BadReg(m) then UNPREDICTABLE;
7242 // if P == '0' && W == '1' then SEE LDRSBT;
7257 // if t == 15 || m == 15 then UNPREDICTABLE;
7261 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
7282 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7292 // address = if index then offset_addr else R[n];
7316 // if wback then R[n] = offset_addr;
7335 if ConditionPassed() then
7337 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
7338 address = if index then offset_addr else R[n];
7340 if wback then R[n] = offset_addr;
7341 if UnalignedSupport() || address<0> = '0' then
7362 // if Rn == '1111' then SEE LDRSH (literal);
7363 // if Rt == '1111' then SEE "Unallocated memory hints";
7374 // if t == 13 then UNPREDICTABLE;
7381 // if Rn == '1111' then SEE LDRSH (literal);
7382 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints";
7383 // if P == '1' && U == '1' && W == '0' then SEE LDRSHT;
7384 // if P == '0' && W == '0' then UNDEFINED;
7398 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
7406 // if Rn == '1111' then SEE LDRSH (literal);
7407 // if P == '0' && W == '1' then SEE LDRSHT;
7420 // if t == 15 || (wback && n == t) then UNPREDICTABLE;
7431 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
7442 // address = if index then offset_addr else R[n];
7461 // if wback then R[n] = offset_addr;
7470 // if UnalignedSupport() || address<0> = '0' then
7495 if ConditionPassed() then
7498 address = if add then (base + imm32) else (base - imm32);
7500 if UnalignedSupport() || address<0> = '0' then
7518 // if Rt == '1111' then SEE "Unallocated memory hints";
7524 // if t == 13 then UNPREDICTABLE;
7539 // if t == 15 then UNPREDICTABLE;
7557 // address = if add then (base + imm32) else (base - imm32);
7575 // if UnalignedSupport() || address<0> = '0' then
7599 if ConditionPassed() then
7602 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7603 address = if index then offset_addr else R[n];
7605 if wback then R[n] = offset_addr;
7606 if UnalignedSupport() || address<0> = '0' then
7629 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
7647 // if Rn == '1111' then SEE LDRSH (literal);
7648 // if Rt == '1111' then SEE "Unallocated memory hints";
7663 // if t == 13 || BadReg(m) then UNPREDICTABLE;
7670 // if P == '0' && W == '1' then SEE LDRSHT;
7685 // if t == 15 || m == 15 then UNPREDICTABLE;
7689 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
7715 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7721 // address = if index then offset_addr else R[n];
7742 // if wback then R[n] = offset_addr;
7751 // if UnalignedSupport() || address<0> = '0' then
7777 if ConditionPassed() then
7808 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
7820 // if d == 15 || m == 15 then UNPREDICTABLE;
7861 if ConditionPassed() then
7892 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
7904 // if d == 15 || m == 15 then UNPREDICTABLE;
7945 if ConditionPassed() then
7976 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
7988 // if d == 15 || m == 15 then UNPREDICTABLE;
8027 if ConditionPassed() then
8057 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
8069 // if d == 15 || m == 15 then UNPREDICTABLE;
8108 if ConditionPassed() then
8110 if !CurrentModeIsPrivileged() || CurrentInstrSet() == InstrSet_ThumbEE then
8113 address = if increment then R[n] else R[n]-8;
8114 if wordhigher then address = address+4;
8117 if wback then R[n] = if increment then R[n]+8 else R[n]-8;
8139 // if n == 15 then UNPREDICTABLE;
8143 // if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
8156 // if n == 15 then UNPREDICTABLE;
8160 // if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
8175 // if n == 15 then UNPREDICTABLE;
8185 // if !CurrentModeIsPrivileged() || CurrentInstrSet() == InstrSet_ThumbEE then
8196 // address = if increment then R[n] else R[n]-8;
8202 // if wordhigher then address = address+4;
8227 // if wback then R[n] = if increment then R[n]+8 else R[n]-8;
8257 if ConditionPassed() then
8260 if d == 15 then // Can only occur for ARM encoding
8264 if setflags then
8286 // if Rd == '1111' && S == '1' then SEE TEQ (immediate);
8298 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8331 if ConditionPassed() then
8335 if d == 15 then // Can only occur for ARM encoding
8339 if setflags then
8370 // if Rd == '1111' && S == '1' then SEE TEQ (register);
8383 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8424 if ConditionPassed() then
8427 if d == 15 then // Can only occur for ARM encoding
8431 if setflags then
8453 // if Rn == '1111' then SEE MOV (immediate);
8497 if ConditionPassed() then
8501 if d == 15 then // Can only occur for ARM encoding
8505 if setflags then
8536 // if Rn == '1111' then SEE MOV (register);
8588 if ConditionPassed() then
8591 if d == 15 then // Can only occur for ARM encoding
8595 if setflags then
8629 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8660 if ConditionPassed() then
8664 if d == 15 then // Can only occur for ARM encoding
8668 if setflags then
8690 // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
8701 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8740 if ConditionPassed() then
8743 if d == 15 then
8747 if setflags then
8767 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8799 if ConditionPassed() then
8803 if d == 15 then
8807 if setflags then
8830 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8869 if ConditionPassed() then
8872 if d == 15 then // Can only occur for ARM encoding
8876 if setflags then
8904 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8936 if ConditionPassed() then
8940 if d == 15 then // Can only occur for ARM encoding
8944 if setflags then
8983 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
9021 if ConditionPassed() then
9025 if setflags then
9056 // if Rd == '1111' && S == '1' then SEE CMP (immediate);
9060 // if Rn == '1101' then SEE SUB (SP minus immediate);
9064 // if d == 13 || (d == 15 && S == '0') || n == 15 then UNPREDICTABLE;
9074 // if Rn == '1111' then SEE ADR;
9078 // if Rn == '1101' then SEE SUB (SP minus immediate);
9112 if ConditionPassed() then
9115 if d == 15 then
9119 if setflags then
9139 // if Rn == '1111' && S == '0' then SEE ADR;
9143 // if Rn == '1101' then SEE SUB (SP minus immediate);
9147 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
9178 if ConditionPassed() then
9235 if ConditionPassed() then
9303 if ConditionPassed() then
9359 if ConditionPassed() then
9431 if ConditionPassed() then
9435 if d == 15 then // Can only occur for ARM encoding
9439 if setflags then
9467 // if d == 13 && (shift_t != SRType_LSL || shift_n > 3) then UNPREDICTABLE;
9471 // if d == 15 || BadReg(m) then UNPREDICTABLE;
9482 // if Rd == ?1111? && S == ?1? then SEE SUBS PC, LR and related instructions;
9530 if ConditionPassed() then
9536 if setflags then
9567 // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
9612 // if setflags then
9628 if ConditionPassed() then
9632 if d == 15 then // Can only occur for ARM encoding
9636 if setflags then
9670 // if Rd == ?1111? && S == ?1? then SEE CMP (register);
9671 // if Rn == ?1101? then SEE SUB (SP minus register);
9681 // if d == 13 || (d == 15 && S == '0') || n == 15 || BadReg(m) then UNPREDICTABLE;
9688 // if Rn == ?1101? then SEE SUB (SP minus register);
9695 // if Rd == ?1111? && S == ?1? then SEE SUBS PC, LR and related instructions;
9724 // if d == 15 then // Can only occur for ARM encoding
9728 // if setflags then
9755 if ConditionPassed() then
9758 if ExclusiveMonitorsPass(address,4) then
9784 // if BadReg(d) || BadReg(t) || n == 15 then UNPREDICTABLE;
9788 // if d == n || d == t then UNPREDICTABLE;
9801 // if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
9805 // if d == n || d == t then UNPREDICTABLE;
9830 // if ExclusiveMonitorsPass(address,4) then
9862 if ConditionPassed() then
9864 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
9865 address = if index then offset_addr else R[n];
9867 if wback then R[n] = offset_addr;
9884 // if P == ?0? && W == ?1? then SEE STRBT;
9895 // if t == 15 then UNPREDICTABLE;
9899 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
9909 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
9920 // address = if index then offset_addr else R[n];
9943 // if wback then R[n] = offset_addr;
9958 if ConditionPassed() then
9960 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
9961 address = if index then offset_addr else R[n];
9962 MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
9963 if wback then R[n] = offset_addr;
9982 // if P == ?0? && W == ?1? then SEE STRT;
9983 // if Rn == ?1101? && P == ?1? && U == ?0? && W == ?1? && imm12 == ?000000000100? then SEE PUSH;
9994 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
10004 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10015 // address = if index then offset_addr else R[n];
10030 // MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
10050 // if wback then R[n] = offset_addr;
10070 if ConditionPassed() then
10072 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10073 address = if index then offset_addr else R[n];
10076 if wback then R[n] = offset_addr;
10094 //if P == ?0? && W == ?0? then SEE ?Related encodings?;
10095 //if Rn == ?1111? then SEE LDRD (literal);
10107 //if wback && (n == t || n == t2) then UNPREDICTABLE;
10111 //if BadReg(t) || BadReg(t2) || t == t2 then UNPREDICTABLE;
10118 //if Rn == ?1111? then SEE LDRD (literal);
10119 //if Rt<0> == ?1? then UNPREDICTABLE;
10133 //if P == ?0? && W == ?1? then UNPREDICTABLE;
10137 //if wback && (n == t || n == t2) then UNPREDICTABLE;
10141 //if t2 == 15 then UNPREDICTABLE;
10151 //offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10162 //address = if index then offset_addr else R[n];
10195 //if wback then R[n] = offset_addr;
10215 if ConditionPassed() then
10217 offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10218 address = if index then offset_addr else R[n];
10221 if wback then R[n] = offset_addr;
10239 // if Rt<0> == ?1? then UNPREDICTABLE;
10253 // if P == ?0? && W == ?1? then UNPREDICTABLE;
10257 // if t2 == 15 || m == 15 || m == t || m == t2 then UNPREDICTABLE;
10261 // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
10265 // if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
10286 // offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10293 // address = if index then offset_addr else R[n];
10322 // if wback then R[n] = offset_addr;
10342 if ConditionPassed() then
10344 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10345 address = if index then offset_addr else R[n];
10348 if wback then R[n] = offset_addr;
10366 // if P == ?0? && W == ?0? then SEE ?Related encodings?;
10378 // if wback && (n == t || n == t2) then UNPREDICTABLE;
10382 // if n == 15 || BadReg(t) || BadReg(t2) then UNPREDICTABLE;
10389 // if Rt<0> == ?1? then UNPREDICTABLE;
10404 // if P == ?0? && W == ?1? then UNPREDICTABLE;
10408 // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
10412 // if t2 == 15 then UNPREDICTABLE;
10429 //offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10436 //address = if index then offset_addr else R[n];
10471 //if wback then R[n] = offset_addr;
10490 if ConditionPassed() then
10492 offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10493 address = if index then offset_addr else R[n];
10496 if wback then R[n] = offset_addr;
10514 // if Rt<0> == ?1? then UNPREDICTABLE;
10529 // if P == ?0? && W == ?1? then UNPREDICTABLE;
10533 // if t2 == 15 || m == 15 then UNPREDICTABLE;
10537 // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
10541 // if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
10565 // offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10572 // address = if index then offset_addr else R[n];
10605 // if wback then R[n] = offset_addr;
10626 if ConditionPassed() then
10628 address = if add then R[n] else R[n]-imm32;
10629 if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10631 if single_regs then
10636 D[d+r] = if BigEndian() then word1:word2 else word2:word1;
10655 // if P == ?0? && U == ?0? && W == ?0? then SEE ?Related encodings?;
10656 // if P == ?0? && U == ?1? && W == ?1? && Rn == ?1101? then SEE VPOP;
10657 // if P == ?1? && W == ?0? then SEE VLDR;
10658 // if P == U && W == ?1? then UNDEFINED;
10676 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10680 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
10688 // if P == ?0? && U == ?0? && W == ?0? then SEE ?Related encodings?;
10689 // if P == ?0? && U == ?1? && W == ?1? && Rn == ?1101? then SEE VPOP;
10690 // if P == ?1? && W == ?0? then SEE VLDR;
10691 // if P == U && W == ?1? then UNDEFINED;
10707 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10711 // if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
10727 // address = if add then R[n] else R[n]-imm32;
10734 // if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10789 // D[d+r] = if BigEndian() then word1:word2 else word2:word1;
10817 if ConditionPassed() then
10819 address = if add then R[n] else R[n]-imm32;
10820 if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10822 if single_regs then
10826 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
10827 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
10847 // if P == ?0? && U == ?0? && W == ?0? then SEE ?Related encodings?;
10848 // if P == ?1? && U == ?0? && W == ?1? && Rn == ?1101? then SEE VPUSH;
10849 // if P == ?1? && W == ?0? then SEE VSTR;
10850 // if P == U && W == ?1? then UNDEFINED;
10868 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10872 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
10880 // if P == ?0? && U == ?0? && W == ?0? then SEE ?Related encodings?;
10881 // if P == ?1? && U == ?0? && W == ?1? && Rn == ?1101? then SEE VPUSH;
10882 // if P == ?1? && W == ?0? then SEE VSTR;
10883 // if P == U && W == ?1? then UNDEFINED;
10899 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10903 // if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
10920 // address = if add then R[n] else R[n]-imm32;
10928 // if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10970 // MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
10971 // MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
11014 if ConditionPassed() then
11016 base = if n == 15 then Align(PC,4) else R[n];
11017 address = if add then (base + imm32) else (base - imm32);
11018 if single_reg then
11023 D[d] = if BigEndian() then word1:word2 else word2:word1;
11074 // base = if n == 15 then Align(PC,4) else R[n];
11081 // address = if add then (base + imm32) else (base - imm32);
11117 // D[d] = if BigEndian() then word1:word2 else word2:word1;
11144 if ConditionPassed() then
11146 address = if add then (R[n] + imm32) else (R[n] - imm32);
11147 if single_reg then
11151 MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11152 MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11178 // if n == 15 && CurrentInstrSet() != InstrSet_ARM then UNPREDICTABLE;
11195 // if n == 15 && CurrentInstrSet() != InstrSet_ARM then UNPREDICTABLE;
11212 // address = if add then (R[n] + imm32) else (R[n] - imm32);
11241 // MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11242 // MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11277 if ConditionPassed() then
11279 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11280 if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11309 // regs = 1; if align<1> == ?1? then UNDEFINED;
11311 // regs = 2; if align == ?11? then UNDEFINED;
11313 // regs = 3; if align<1> == ?1? then UNDEFINED;
11346 // alignment = if align == ?00? then 1 else 4 << UInt(align);
11366 // if d+regs > 32 then UNPREDICTABLE;
11383 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11389 // if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11443 if ConditionPassed() then
11445 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11446 if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11471 // if size == ?11? then SEE VLD1 (single element to all lanes);
11477 // if index_align<0> != ?0? then UNDEFINED;
11489 // if index_align<1> != ?0? then UNDEFINED;
11498 // alignment = if index_align<0> == ?0? then 1 else 2;
11506 // if index_align<2> != ?0? then UNDEFINED;
11510 // if index_align<1:0> != ?00? && index_align<1:0> != ?11? then UNDEFINED;
11519 // alignment = if index_align<1:0> == ?00? then 1 else 4;
11534 // wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE;
11555 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11561 // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11619 if ConditionPassed() then
11621 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11622 if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11655 // regs = 1; if align<1> == ?1? then UNDEFINED;
11662 // regs = 2; if align == ?11? then UNDEFINED;
11669 // regs = 3; if align<1> == ?1? then UNDEFINED;
11681 // alignment = if align == ?00? then 1 else 4 << UInt(align);
11701 // if d+regs > 32 then UNPREDICTABLE; if n == 15 then UNPREDICTABLE;
11722 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11728 // if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11782 if ConditionPassed() then
11784 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11785 if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11811 // if size == ?11? then UNDEFINED;
11818 // if index_align<0> != ?0? then UNDEFINED;
11829 // if index_align<1> != ?0? then UNDEFINED;
11838 // alignment = if index_align<0> == ?0? then 1 else 2;
11846 // if index_align<2> != ?0? then UNDEFINED;
11850 // if index_align<1:0> != ?00? && index_align<1:0> != ?11? then UNDEFINED;
11859 // alignment = if index_align<1:0> == ?00? then 1 else 4;
11874 // wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE;
11894 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11900 // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11944 if ConditionPassed() then
11946 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11947 if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11972 //if size == ?11? || (size == ?00? && a == ?1?) then UNDEFINED;
11977 //ebytes = 1 << UInt(size); elements = 8 DIV ebytes; regs = if T == ?0? then 1 else 2;
11985 //alignment = if a == ?0? then 1 else ebytes;
12000 //if d+regs > 32 then UNPREDICTABLE; if n == 15 then UNPREDICTABLE;
12020 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
12026 // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
12076 if ConditionPassed() then
12078 if CurrentInstrSet() == InstrSet_ThumbEE then
12080 operand2 = if register_form then Shift(R[m], shift_t, shift_n, APSR.C) else imm32;
12113 // if CurrentInstrSet() == InstrSet_ThumbEE then UNPREDICTABLE
12120 // if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
12150 // operand2 = if register_form then Shift(R[m], shift_t, shift_n, APSR.C) else imm32;
12286 // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH;
12548 // If Then makes up to four following instructions conditional.
12550 // The next 5 opcode _must_ come before the if then instruction
12924 // If we are ignoring conditions, then always return true.
13336 // if d == 15 then // Can only occur for encoding A1
13340 // if setflags then
