Lines Matching refs:__xmm_reg
396 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0';
397 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1';
398 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2';
399 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3';
400 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4';
401 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5';
402 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6';
403 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7';
413 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
414 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
415 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
416 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3';
417 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4';
418 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5';
419 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
420 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
466 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
467 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
468 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
469 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
470 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
471 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
472 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
473 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
1027 #define FPU_SIZE_XMM(reg) (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg.__xmm_reg))
1338 case fpu_xmm0: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg, 16); return true;
1339 case fpu_xmm1: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg, 16); return true;
1340 case fpu_xmm2: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg, 16); return true;
1341 case fpu_xmm3: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg, 16); return true;
1342 case fpu_xmm4: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg, 16); return true;
1343 case fpu_xmm5: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg, 16); return true;
1344 case fpu_xmm6: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg, 16); return true;
1345 case fpu_xmm7: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg, 16); return true;
1348 memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, 16); \
1349 memcpy((&value->value.uint8) + 16, m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, 16);
1385 case fpu_xmm0: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, 16); return true;
1386 case fpu_xmm1: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, 16); return true;
1387 case fpu_xmm2: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, 16); return true;
1388 case fpu_xmm3: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, 16); return true;
1389 case fpu_xmm4: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, 16); return true;
1390 case fpu_xmm5: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, 16); return true;
1391 case fpu_xmm6: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, 16); return true;
1392 case fpu_xmm7: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, 16); return true;
1485 case fpu_xmm0: memcpy(m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg, &value->value.uint8, 16); success = true; break;
1486 case fpu_xmm1: memcpy(m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg, &value->value.uint8, 16); success = true; break;
1487 case fpu_xmm2: memcpy(m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg, &value->value.uint8, 16); success = true; break;
1488 case fpu_xmm3: memcpy(m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg, &value->value.uint8, 16); success = true; break;
1489 case fpu_xmm4: memcpy(m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg, &value->value.uint8, 16); success = true; break;
1490 case fpu_xmm5: memcpy(m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg, &value->value.uint8, 16); success = true; break;
1491 case fpu_xmm6: memcpy(m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg, &value->value.uint8, 16); success = true; break;
1492 case fpu_xmm7: memcpy(m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg, &value->value.uint8, 16); success = true; break;
1495 memcpy(m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, &value->value.uint8, 16); \
1496 memcpy(m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, (&value->value.uint8) + 16, 16);
1532 case fpu_xmm0: memcpy(m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, &value->value.uint8, 16); success = true; break;
1533 case fpu_xmm1: memcpy(m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, &value->value.uint8, 16); success = true; break;
1534 case fpu_xmm2: memcpy(m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, &value->value.uint8, 16); success = true; break;
1535 case fpu_xmm3: memcpy(m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, &value->value.uint8, 16); success = true; break;
1536 case fpu_xmm4: memcpy(m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, &value->value.uint8, 16); success = true; break;
1537 case fpu_xmm5: memcpy(m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, &value->value.uint8, 16); success = true; break;
1538 case fpu_xmm6: memcpy(m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, &value->value.uint8, 16); success = true; break;
1539 case fpu_xmm7: memcpy(m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, &value->value.uint8, 16); success = true; break;
