Lines Matching refs:__xmm_reg
305 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0';
306 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1';
307 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2';
308 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3';
309 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4';
310 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5';
311 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6';
312 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7';
313 m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8';
314 m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9';
315 m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A';
316 m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B';
317 m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C';
318 m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D';
319 m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E';
320 m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F';
322 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
323 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
324 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
325 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3';
326 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4';
327 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5';
328 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
329 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
330 m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8';
331 m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9';
332 m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A';
333 m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B';
334 m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C';
335 m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D';
336 m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E';
337 m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F';
389 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
390 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
391 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
392 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
393 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
394 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
395 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
396 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
397 m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8';
398 m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9';
399 m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A';
400 m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B';
401 m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C';
402 m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D';
403 m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E';
404 m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F';
1270 #define FPU_SIZE_XMM(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__xmm_reg))
