Lines Matching refs:m_state
124 return m_state.context.gpr.__rip;
135 m_state.context.gpr.__rip = value;
146 return m_state.context.gpr.__rsp;
156 if (force || m_state.GetError(e_regSetGPR, Read))
159 m_state.context.gpr.__rax = ('a' << 8) + 'x';
160 m_state.context.gpr.__rbx = ('b' << 8) + 'x';
161 m_state.context.gpr.__rcx = ('c' << 8) + 'x';
162 m_state.context.gpr.__rdx = ('d' << 8) + 'x';
163 m_state.context.gpr.__rdi = ('d' << 8) + 'i';
164 m_state.context.gpr.__rsi = ('s' << 8) + 'i';
165 m_state.context.gpr.__rbp = ('b' << 8) + 'p';
166 m_state.context.gpr.__rsp = ('s' << 8) + 'p';
167 m_state.context.gpr.__r8 = ('r' << 8) + '8';
168 m_state.context.gpr.__r9 = ('r' << 8) + '9';
169 m_state.context.gpr.__r10 = ('r' << 8) + 'a';
170 m_state.context.gpr.__r11 = ('r' << 8) + 'b';
171 m_state.context.gpr.__r12 = ('r' << 8) + 'c';
172 m_state.context.gpr.__r13 = ('r' << 8) + 'd';
173 m_state.context.gpr.__r14 = ('r' << 8) + 'e';
174 m_state.context.gpr.__r15 = ('r' << 8) + 'f';
175 m_state.context.gpr.__rip = ('i' << 8) + 'p';
176 m_state.context.gpr.__rflags = ('f' << 8) + 'l';
177 m_state.context.gpr.__cs = ('c' << 8) + 's';
178 m_state.context.gpr.__fs = ('f' << 8) + 's';
179 m_state.context.gpr.__gs = ('g' << 8) + 's';
180 m_state.SetError(e_regSetGPR, Read, 0);
183 m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, &count));
192 m_state.GetError(e_regSetGPR, Read),
193 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx,
194 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi,
195 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8,
196 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11,
197 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14,
198 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags,
199 m_state.context.gpr.__cs,m_state.context.gpr.__fs, m_state.context.gpr.__gs);
226 // m_state.GetError(e_regSetGPR, Read),
227 // m_state.context.gpr.__rax,
228 // m_state.context.gpr.__rbx,
229 // m_state.context.gpr.__rcx,
230 // m_state.context.gpr.__rdx,
231 // m_state.context.gpr.__rdi,
232 // m_state.context.gpr.__rsi,
233 // m_state.context.gpr.__rbp,
234 // m_state.context.gpr.__rsp,
235 // m_state.context.gpr.__r8,
236 // m_state.context.gpr.__r9,
237 // m_state.context.gpr.__r10,
238 // m_state.context.gpr.__r11,
239 // m_state.context.gpr.__r12,
240 // m_state.context.gpr.__r13,
241 // m_state.context.gpr.__r14,
242 // m_state.context.gpr.__r15,
243 // m_state.context.gpr.__rip,
244 // m_state.context.gpr.__rflags,
245 // m_state.context.gpr.__cs,
246 // m_state.context.gpr.__fs,
247 // m_state.context.gpr.__gs);
250 return m_state.GetError(e_regSetGPR, Read);
259 if (force || m_state.GetError(e_regSetFPU, Read))
264 m_state.context.fpu.avx.__fpu_reserved[0] = -1;
265 m_state.context.fpu.avx.__fpu_reserved[1] = -1;
266 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
267 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
268 m_state.context.fpu.avx.__fpu_ftw = 1;
269 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
270 m_state.context.fpu.avx.__fpu_fop = 2;
271 m_state.context.fpu.avx.__fpu_ip = 3;
272 m_state.context.fpu.avx.__fpu_cs = 4;
273 m_state.context.fpu.avx.__fpu_rsrv2 = 5;
274 m_state.context.fpu.avx.__fpu_dp = 6;
275 m_state.context.fpu.avx.__fpu_ds = 7;
276 m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX;
277 m_state.context.fpu.avx.__fpu_mxcsr = 8;
278 m_state.context.fpu.avx.__fpu_mxcsrmask = 9;
284 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a';
285 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b';
286 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c';
287 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd';
288 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e';
289 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f';
290 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g';
291 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h';
295 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
296 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
297 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
298 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
299 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
300 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
301 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
302 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
305 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0';
306 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1';
307 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2';
308 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3';
309 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4';
310 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5';
311 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6';
312 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7';
313 m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8';
314 m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9';
315 m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A';
316 m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B';
317 m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C';
318 m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D';
319 m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E';
320 m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F';
322 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
323 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
324 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
325 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3';
326 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4';
327 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5';
328 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
329 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
330 m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8';
331 m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9';
332 m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A';
333 m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B';
334 m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C';
335 m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D';
336 m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E';
337 m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F';
339 for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
340 m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN;
341 m_state.context.fpu.avx.__fpu_reserved1 = -1;
342 for (i=0; i<sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
343 m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
344 m_state.SetError(e_regSetFPU, Read, 0);
348 m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
349 m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
350 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
351 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
352 m_state.context.fpu.no_avx.__fpu_ftw = 1;
353 m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
354 m_state.context.fpu.no_avx.__fpu_fop = 2;
355 m_state.context.fpu.no_avx.__fpu_ip = 3;
356 m_state
357 m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
358 m_state.context.fpu.no_avx.__fpu_dp = 6;
359 m_state.context.fpu.no_avx.__fpu_ds = 7;
360 m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
361 m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
362 m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
368 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
369 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
370 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
371 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
372 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
373 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
374 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
375 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
379 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
380 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
381 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
382 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
383 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
384 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
385 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
386 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
389 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
390 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
391 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
392 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
393 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
394 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
395 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
396 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
397 m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8';
398 m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9';
399 m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A';
400 m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B';
401 m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C';
402 m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D';
403 m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E';
404 m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F';
406 for (i=0; i<sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i)
407 m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
408 m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
409 m_state.SetError(e_regSetFPU, Read, 0);
417 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, &count));
420 e_regSetWordSizeAVX, m_state.GetError(e_regSetFPU, Read));
425 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, &count));
428 e_regSetWordSizeFPU, m_state.GetError(e_regSetFPU, Read));
432 return m_state.GetError(e_regSetFPU, Read);
438 if (force || m_state.GetError(e_regSetEXC, Read))
441 m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, &count));
443 return m_state.GetError(e_regSetEXC, Read);
452 m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, e_regSetWordSizeGPR));
461 m_state.GetError(e_regSetGPR, Write),
462 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx,
463 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi,
464 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8,
465 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11,
466 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14,
467 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags,
468 m_state.context.gpr.__cs, m_state.context.gpr.__fs, m_state.context.gpr.__gs);
469 return m_state.GetError(e_regSetGPR, Write);
477 m_state.SetError(e_regSetFPU, Write, 0);
478 return m_state.GetError(e_regSetFPU, Write);
484 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, e_regSetWordSizeAVX));
485 return m_state.GetError(e_regSetFPU, Write);
489 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, e_regSetWordSizeFPU));
490 return m_state.GetError(e_regSetFPU, Write);
498 m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, e_regSetWordSizeEXC));
499 return m_state.GetError(e_regSetEXC, Write);
505 if (force || m_state.GetError(e_regSetDBG, Read))
508 m_state.SetError(e_regSetDBG, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, &count));
510 return m_state.GetError(e_regSetDBG, Read);
516 m_state.SetError(e_regSetDBG, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG));
519 kern_return_t kret = ::task_set_state(m_thread->Process()->Task().TaskPort(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG);
523 return m_state.GetError(e_regSetDBG, Write);
542 DBG &debug_state = m_state.context.dbg;
562 m_state.InvalidateAllRegisterStates();
616 if (m_state.context.gpr.__rip > 0)
618 m_state.context.gpr.__rip = pc;
806 m_2pc_dbg_checkpoint = m_state.context.dbg;
813 m_state.context.dbg = m_2pc_dbg_checkpoint;
860 DBG &debug_state = m_state.context.dbg;
881 m_state.context.dbg = GetDBGCheckpoint();
899 DBG &debug_state = m_state.context.dbg;
914 m_state.context.dbg = GetDBGCheckpoint();
929 DBG &debug_state = m_state.context.dbg;
955 m_state.context.gpr.__rflags |= trace_bit;
957 m_state.context.gpr.__rflags &= ~trace_bit;
960 return m_state.GetError(e_regSetGPR, Read);
1635 value->value.uint64 = ((uint64_t*)(&m_state.context.gpr))[reg];
1645 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)); return true;
1646 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)); return true;
1647 case fpu_ftw: value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw; return true;
1648 case fpu_fop: value->value.uint16 = m_state.context.fpu.avx.__fpu_fop; return true;
1649 case fpu_ip: value->value.uint32 = m_state.context.fpu.avx.__fpu_ip; return true;
1650 case fpu_cs: value->value.uint16 = m_state.context.fpu.avx.__fpu_cs; return true;
1651 case fpu_dp: value->value.uint32 = m_state.context.fpu.avx.__fpu_dp; return true;
1652 case fpu_ds: value->value.uint16 = m_state.context.fpu.avx.__fpu_ds; return true;
1653 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr; return true;
1654 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask; return true;
1664 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), 10);
1683 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), 16);
1702 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16);
1703 memcpy((&value->value.uint8) + 16, &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16);
1711 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); return true;
1712 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); return true;
1713 case fpu_ftw: value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw; return true;
1714 case fpu_fop: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; return true;
1715 case fpu_ip: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; return true;
1716 case fpu_cs: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; return true;
1717 case fpu_dp: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; return true;
1718 case fpu_ds: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; return true;
1719 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; return true;
1720 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; return true;
1730 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), 10);
1749 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16);
1758 case exc_trapno: value->value.uint32 = m_state.context.exc.__trapno; return true;
1759 case exc_err: value->value.uint32 = m_state.context.exc.__err; return true;
1760 case exc_faultvaddr:value->value.uint64 = m_state.context.exc.__faultvaddr; return true;
1814 ((uint64_t*)(&m_state.context.gpr))[reg] = value->value.uint64;
1824 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) = value->value.uint16; success = true; break;
1825 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) = value->value.uint16; success = true; break;
1826 case fpu_ftw: m_state.context.fpu.avx.__fpu_ftw = value->value.uint8; success = true; break;
1827 case fpu_fop: m_state.context.fpu.avx.__fpu_fop = value->value.uint16; success = true; break;
1828 case fpu_ip: m_state.context.fpu.avx.__fpu_ip = value->value.uint32; success = true; break;
1829 case fpu_cs: m_state.context.fpu.avx.__fpu_cs = value->value.uint16; success = true; break;
1830 case fpu_dp: m_state.context.fpu.avx.__fpu_dp = value->value.uint32; success = true; break;
1831 case fpu_ds: m_state.context.fpu.avx.__fpu_ds = value->value.uint16; success = true; break;
1832 case fpu_mxcsr: m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32; success = true; break;
1833 case fpu_mxcsrmask: m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32; success = true; break;
1843 memcpy (&m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10);
1863 memcpy (&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16);
1883 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), &value->value.uint8, 16);
1884 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), (&value->value.uint8) + 16, 16);
1892 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = value->value.uint16; success = true; break;
1893 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = value->value.uint16; success = true; break;
1894 case fpu_ftw: m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8; success = true; break;
1895 case fpu_fop: m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; success = true; break;
1896 case fpu_ip: m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; success = true; break;
1897 case fpu_cs: m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; success = true; break;
1898 case fpu_dp: m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; success = true; break;
1899 case fpu_ds: m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; success = true; break;
1900 case fpu_mxcsr: m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; success = true; break;
1901 case fpu_mxcsrmask: m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; success = true; break;
1911 memcpy (&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10);
1931 memcpy (&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16);
1941 case exc_trapno: m_state.context.exc.__trapno = value->value.uint32; success = true; break;
1942 case exc_err: m_state.context.exc.__err = value->value.uint32; success = true; break;
1943 case exc_faultvaddr:m_state.context.exc.__faultvaddr = value->value.uint64; success = true; break;
1958 nub_size_t size = sizeof (m_state.context);
1987 ::memcpy (buf, &m_state.context, size);
1998 nub_size_t size = sizeof (m_state.context);
2007 ::memcpy (&m_state.context, buf, size);
2056 return m_state.RegsAreValid(set);
