Lines Matching full:pass
63 cl::desc("Disable Loop Strength Reduction Pass"));
69 cl::desc("Disable Copy Propagation pass"));
73 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
75 cl::desc("Print LLVM IR input to isel pass"));
86 cl::value_desc("pass-name"), cl::init("option-unspecified"));
91 // wouldn't be part of the standard pass pipeline, and the target would just add
92 // a PostRA scheduling pass wherever it wants.
105 /// simple binary flags that either suppress the pass or do nothing.
116 /// is adding the pass.
118 /// StandardID is the pass identified in the standard pass pipeline and provided
120 /// directly adds its own pass, but in that case we harmlessly fall through.
122 /// TargetID is the pass that the target has configured to override StandardID.
125 /// pass to run. This allows multiple options to control a single pass depending
126 /// on where in the pipeline that pass is added.
176 "Target Pass Configuration", false, false)
179 // Pseudo Pass IDs.
188 // that are part of a standard pass pipeline without overridding the entire
189 // pipeline. This mechanism allows target options to inherit a standard pass's
190 // user interface. For example, a target may disable a standard pass by
191 // default by substituting a pass ID of zero, and the user may still enable
192 // that standard pass with an explicit command line option.
195 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
206 // Out of line constructor provides default values for pass options and
217 // including this pass itself.
220 // Substitute Pseudo Pass IDs for real ones.
225 /// Insert InsertedPassID pass after TargetPassID.
232 "Insert a pass after itself!");
237 /// createPassConfig - Create a pass configuration object to be used by
269 /// Add a pass to the PassManager if that pass is supposed to be run. If the
271 /// a later pass or that it should stop after an earlier pass, then do not add
272 /// the pass. Finally, compare the current pass against the StartAfter
274 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
277 // Cache the Pass ID here in case the pass manager finds this pass is
279 // Fundamentally, once we add the pass to the manager, we no longer own it
285 // Construct banner message before PM->add() as that may delete the pass.
303 report_fatal_error("Cannot stop compilation after pass that is not run");
306 /// Add a CodeGen pass at this point in the pipeline after checking for target
309 /// addPass cannot return a pointer to the pass instance because is internal the
318 Pass *P;
322 P = Pass::createPass(FinalPtr.getID());
324 llvm_unreachable("Pass ID not registered");
329 // Add the passes after the pass P if there is any.
334 assert((*I).second.isValid() && "Illegal Pass ID!");
335 Pass *NP;
339 NP = Pass::createPass((*I).second.getID());
340 assert(NP && "Pass ID not registered");
389 // TODO: add a pass insertion point here
423 // add both preparation passes. Each pass will only actually run if it
431 // The lower invoke pass may create unreachable code. Remove it.
437 /// Add pass to prepare the LLVM IR for code generation. This should be done
471 /// targets have the flexibility to change pass order within a stage by
473 /// technique has maintainability tradeoffs because alternate pass orders are
474 /// not well supported. addPre/Post works better if the target pass is easily
475 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
478 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
479 /// before/after any target-independent pass. But it's currently overkill.
483 // Insert a machine instr printer pass after the specified pass.
492 assert (TPI && IPI && "Pass ID not registered!");
533 // Expand pseudo instructions before second scheduling pass.
539 // Second pass scheduler.
573 // This pass merges large allocas. StackSlotColoring is a different pass
603 /// Register Allocation Pass Configuration
618 /// A dummy default pass factory indicates whether the register allocator is
634 /// Instantiate the default register allocator pass for this target for either
635 /// the optimized or unoptimized allocation path. This will be added to the pass
639 /// A target that uses the standard regalloc pass order for fast or optimized
649 /// Find and instantiate the register allocation pass requested by this target
656 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
669 // With no -regalloc= override, ask the target for a regalloc pass.
696 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
716 // Add the selected register allocation pass.
738 /// Post RegAlloc Pass Configuration
766 // Run a separate pass to collect block placement statistics.
