Lines Matching full:intf
254 InterferenceCache::Cursor Intf;
263 Intf.setPhysReg(Cache, Reg);
728 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
729 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
732 if (getStage(*Intf) == RS_Done)
741 (Intf->isSpillable() ||
743 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
745 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
754 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
757 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
764 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
769 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
770 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
805 LiveInterval *Intf = Intfs[i];
807 if (!VRM->hasPhys(Intf->reg))
809 Matrix->unassign(*Intf);
810 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
811 VirtReg.isSpillable() < Intf->isSpillable()) &&
813 ExtraRegInfo[Intf->reg].Cascade = Cascade;
815 NewVRegs.push_back(Intf->reg);
900 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
912 Intf.moveToBlock(BC.Number);
917 if (!Intf.hasInterference())
925 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
927 else if (Intf.first() < BI.FirstInstr)
929 else if (Intf.first() < BI.LastInstr)
935 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
937 else if (Intf.last() > BI.LastInstr)
939 else if (Intf.last() > BI.FirstInstr)
958 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
967 Intf.moveToBlock(Number);
969 if (!Intf.hasInterference()) {
983 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
989 if (Intf.last() >= SA->getLastSplitPoint(Number))
1041 addThroughConstraints(Cand.Intf, NewBlocks);
1075 // The static split cost will be zero since Cand.Intf reports no interference.
1077 if (!addSplitConstraints(Cand.Intf, Cost)) {
1148 Cand.Intf.moveToBlock(Number);
1149 if (Cand.Intf.hasInterference()) {
1199 Cand.Intf.moveToBlock(Number);
1200 IntfIn = Cand.Intf.first();
1208 Cand.Intf.moveToBlock(Number);
1209 IntfOut = Cand.Intf.last();
1248 Cand.Intf.moveToBlock(Number);
1249 IntfIn = Cand.Intf.first();
1256 Cand.Intf.moveToBlock(Number);
1257 IntfOut = Cand.Intf.last();
1380 if (!addSplitConstraints(Cand.Intf, Cost)) {
1984 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
1985 // If Intf is done and sit on the same register class as VirtReg,
1987 if ((getStage(*Intf) == RS_Done &&
1988 MRI->getRegClass(Intf->reg) == CurRC) ||
1989 FixedRegisters.count(Intf->reg)) {
1993 RecoloringCandidates.insert(Intf);
