Lines Matching defs:SU
207 /// the exit SU to the register defs and use list. This is because we want to
250 /// MO is an operand of SU's instruction that defines a physical register. Add
251 /// data dependencies from SU to any uses of the physical register.
252 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
253 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
264 SUnit *UseSU = I->SU;
265 if (UseSU == SU)
274 Dep = SDep(SU, SDep::Artificial);
278 SU->hasPhysRegDefs = true;
279 Dep = SDep(SU, SDep::Data, *Alias);
283 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
286 ST.adjustSchedDependency(SU, UseSU, Dep);
295 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
296 MachineInstr *MI = SU->getInstr();
311 SUnit *DefSU = I->SU;
314 if (DefSU != SU &&
318 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
320 SDep Dep(SU, Kind, /*Reg=*/*Alias);
330 SU->hasPhysRegUses = true;
334 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
339 addPhysRegDataDeps(SU, OperIdx);
348 } else if (SU->isCall) {
359 if (!I->SU->isCall)
366 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
376 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
377 const MachineInstr *MI = SU->getInstr();
395 VRegDefs.insert(VReg2SUnit(Reg, SU));
397 SUnit *DefSU = DefI->SU;
398 if (DefSU != SU && DefSU != &ExitSU) {
399 SDep Dep(SU, SDep::Output, Reg);
404 DefI->SU = SU;
414 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
415 MachineInstr *MI = SU->getInstr();
421 if (UI->SU == SU)
425 VRegUses.insert(VReg2SUnit(Reg, SU
449 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
450 SU->addPred(dep);
456 if (DefI != VRegDefs.end() && DefI->SU != SU)
457 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
627 /// This function assumes that "downward" from SU there exist
629 /// checks whether SU can be aliasing any node dominated
632 const DataLayout &DL, SUnit *SU, SUnit *ExitSU,
635 if (!SU)
643 if (SU == *I)
645 if (MIsNeedChainEdge(AA, MFI, DL, SU->getInstr(), (*I)->getInstr())) {
646 SDep Dep(SU, SDep::MayAliasMem);
656 iterateChainSucc(AA, MFI, DL, SU, J->getSUnit(), ExitSU, &Depth,
662 /// otherwise remember the rejected SU.
679 DEBUG(dbgs() << "\tReject chain dep between SU("
680 << SUa->NodeNum << ") and SU("
706 SUnit *SU = newSUnit(MI);
707 MISUnitMap[MI] = SU;
709 SU->isCall = MI->isCall();
710 SU->isCommutable = MI->isCommutable();
712 // Assign the Latency field of SU using target-provided information.
713 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
724 const MCSchedClassDesc *SC = getSchedClass(SU);
730 SU->hasReservedResource = true;
733 SU->isUnbuffered = true;
810 SUnit *SU = MISUnitMap[MI];
811 assert(SU && "No SUnit mapped to this MI");
814 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : nullptr;
833 addPhysRegDeps(SU, j);
838 addVRegDefDeps(SU, j);
841 addVRegUseDeps(SU, j);
850 if (SU->NumSuccs == 0 && SU->Latency > 1
852 SDep Dep(SU, SDep::Artificial);
853 Dep.setLatency(SU->Latency - 1);
873 I->second[i]->addPred(SDep(SU, SDep::Barrier));
879 SDep Dep(SU, SDep::Barrier);
884 // Add SU to the barrier chain.
886 BarrierChain->addPred(SDep(SU, SDep::Barrier));
887 BarrierChain = SU;
890 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU, RejectMemNodes,
898 // Chain all possibly aliasing memory references through SU.
903 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU, AliasChain,
906 AliasChain = SU;
908 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
914 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
920 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
923 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU, RejectMemNodes,
931 // SU and barrier _could_ be reordered, they should not. In addition,
934 BarrierChain->addPred(SDep(SU, SDep::Barrier));
961 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
967 I->second.push_back(SU);
972 AliasMemDefs[V].push_back(SU);
976 NonAliasMemDefs[V].push_back(SU);
986 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
996 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
1001 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU, AliasChain,
1004 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU, RejectMemNodes,
1020 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
1023 PendingLoads.push_back(SU);
1044 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
1047 AliasMemUses[V].push_back(SU);
1049 NonAliasMemUses[V].push_back(SU);
1052 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU,
1056 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU, AliasChain,
1059 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1211 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1213 SU->getInstr()->dump();
1217 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1220 if (SU == &EntrySU)
1222 else if (SU == &ExitSU)
1225 SU->getInstr()->print(oss, /*SkipOpers=*/true);
1272 bool isVisited(const SUnit *SU) const {
1273 return R.DFSNodeData[SU->NodeNum].SubtreeID
1279 void visitPreorder(const SUnit *SU) {
1280 R.DFSNodeData[SU->NodeNum].InstrCount =
1281 SU->getInstr()->isTransient() ? 0 : 1;
1287 void visitPostorderNode(const SUnit *SU) {
1290 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1291 RootData RData(SU->NodeNum);
1292 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1299 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1301 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1306 joinPredSubtree(*PI, SU, /*CheckLimit=*/false);
1313 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1324 RootSet[SU->NodeNum] = RData;
1364 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1439 void follow(const SUnit *SU) {
1440 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1459 static bool hasDataSucc(const SUnit *SU) {
1461 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) {
1477 const SUnit *SU = &*SI;
1478 if (Impl.isVisited(SU) || hasDataSucc(SU))
1482 Impl.visitPreorder(SU);
1483 DFS.follow(SU);
