Lines Matching defs:N0
249 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference);
251 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference);
319 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
320 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
323 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
342 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
344 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
687 SDValue N0, N1, N2;
688 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
768 SDValue N0, SDValue N1) {
769 EVT VT = N0.getValueType();
770 if (N0.getOpcode() == Opc) {
771 if (SDNode *L = isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
775 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
778 if (N0.hasOneUse()) {
781 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
785 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
792 if (SDNode *L = isConstantIntBuildVectorOrConstantInt(N0)) {
801 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N1.getOperand(0), N0);
998 SDValue N0 = Op.getOperand(0);
999 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1006 if (N0 == N1)
1019 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1056 SDValue N0 = Op.getOperand(0);
1058 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
1060 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
1062 N0 = PromoteOperand(N0, PVT, Replace);
1063 if (!N0.getNode())
1066 AddToWorklist(N0.getNode());
1068 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1074 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1441 SDValue N0 = N->getOperand(0);
1445 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1446 SDValue Ops[] = {N1, N0};
1576 SDValue N0 = N->getOperand(0);
1578 EVT VT = N0.getValueType();
1587 return N0;
1588 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1593 if (N0.getOpcode() == ISD::UNDEF)
1594 return N0;
1598 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1603 if (isConstantIntBuildVectorOrConstantInt(N0) &&
1605 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1608 return N0;
1610 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1617 if (N1C && N0.getOpcode() == ISD::SUB)
1618 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1622 N0.getOperand(1));
1624 if (SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1))
1627 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1628 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1629 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1633 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1635 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1638 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1639 return N0.getOperand(0);
1642 N0 == N1.getOperand(1).getOperand(0))
1647 N0 == N1.getOperand(1).getOperand(1))
1653 N0 == N1.getOperand(0).getOperand(1))
1658 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1659 SDValue N00 = N0.getOperand(0);
1660 SDValue N01 = N0.getOperand(1);
1666 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1677 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1686 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1697 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1701 if (N0.getOpcode() == ISD::SHL &&
1702 N0.getOperand(0).getOpcode() == ISD::SUB)
1704 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1708 N0.getOperand(0).getOperand(1),
1709 N0.getOperand(1)));
1726 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1727 N0.getOperand(0).getValueType() == MVT::i1 &&
1730 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1741 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
1749 SDValue N0 = N->getOperand(0);
1751 EVT VT = N0.getValueType();
1755 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1760 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1763 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1767 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1773 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1781 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1790 SDValue N0 = N->getOperand(0);
1795 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1799 N1, N0, CarryIn);
1803 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1821 SDValue N0 = N->getOperand(0);
1823 EVT VT = N0.getValueType();
1832 return N0;
1837 if (N0 == N1)
1840 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1846 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1850 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1852 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1855 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1856 return N0.getOperand(1);
1858 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1859 return N0.getOperand(0);
1870 if (N0.getOpcode() == ISD::ADD &&
1871 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1872 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1873 N0.getOperand(1).getOperand(0) == N1)
1874 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1875 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1877 if (N0.getOpcode() == ISD::ADD &&
1878 N0.getOperand(1).getOpcode() == ISD::ADD &&
1879 N0.getOperand(1).getOperand(1) == N1)
1881 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1883 if (N0.getOpcode() == ISD::SUB &&
1884 N0.getOperand(1).getOpcode() == ISD::SUB &&
1885 N0.getOperand(1).getOperand(1) == N1)
1887 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1890 if (N0.getOpcode() == ISD::UNDEF)
1891 return N0;
1896 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1917 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
1925 SDValue N0 = N->getOperand(0);
1927 EVT VT = N0.getValueType();
1931 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1936 if (N0 == N1)
1942 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1945 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1950 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1958 SDValue N0 = N->getOperand(0);
1964 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1970 SDValue N0 = N->getOperand(0);
1972 EVT VT = N0.getValueType();
1975 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1986 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
1989 N0IsConst = isa<ConstantSDNode>(N0);
1991 ConstValue0 = cast<ConstantSDNode>(N0)->getAPIntValue();
1999 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
2002 if (isConstantIntBuildVectorOrConstantInt(N0) &&
2004 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
2014 return N0;
2018 DAG.getConstant(0, VT), N0);
2021 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
2023 getShiftAmountTy(N0.getValueType())));
2031 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
2033 getShiftAmountTy(N0.getValueType()))));
2038 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
2039 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2040 isa<ConstantSDNode>(N0.getOperand(1)))) {
2042 N1, N0.getOperand(1));
2045 N0.getOperand(0), C3);
2053 if (N0.getOpcode() == ISD::SHL &&
2054 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2055 isa<ConstantSDNode>(N0.getOperand(1))) &&
2056 N0.getNode()->hasOneUse()) {
2057 Sh = N0; Y = N1;
2061 Sh = N1; Y = N0;
2073 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
2074 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2075 isa<ConstantSDNode>(N0.getOperand(1))))
2077 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2078 N0.getOperand(0), N1),
2080 N0.getOperand(1), N1));
2083 if (SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1))
2090 SDValue N0 = N->getOperand(0);
2100 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2106 return N0;
2110 DAG.getConstant(0, VT), N0);
2114 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2116 N0, N1);
2136 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
2138 getShiftAmountTy(N0.getValueType())));
2141 // Add (N0 < 0) ? abs2 - 1 : 0;
2146 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
2169 if (N0.getOpcode() == ISD::UNDEF)
2179 SDValue N0 = N->getOperand(0);
2189 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2195 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2197 getShiftAmountTy(N0.getValueType())));
2209 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2220 if (N0.getOpcode() == ISD::UNDEF)
2230 SDValue N0 = N->getOperand(0);
2235 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2242 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2243 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2249 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2255 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2262 if (N0.getOpcode() == ISD::UNDEF)
2272 SDValue N0 = N->getOperand(0);
2277 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2283 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2294 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2302 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2308 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2315 if (N0.getOpcode() == ISD::UNDEF)
2325 SDValue N0 = N->getOperand(0);
2336 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2337 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2338 getShiftAmountTy(N0.getValueType())));
2340 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2350 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2352 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2363 SDValue N0 = N->getOperand(0);
2374 return DAG.getConstant(0, N0.getValueType());
2376 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2386 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2388 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2470 // Compute the low part as N0.
2500 // Compute the low part as N0.
2546 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2547 EVT VT = N0.getValueType();
2548 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2551 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2562 EVT Op0VT = N0.getOperand(0).getValueType();
2563 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2564 N0.getOpcode() == ISD::SIGN_EXTEND ||
2565 N0.getOpcode() == ISD::BSWAP ||
2567 (N0.getOpcode() == ISD::ANY_EXTEND &&
2569 (N0.getOpcode() == ISD::TRUNCATE &&
2576 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2577 N0.getOperand(0).getValueType(),
2578 N0.getOperand(0), N1.getOperand(0));
2580 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2587 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2588 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2589 N0.getOperand(1) == N1.getOperand(1)) {
2590 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2591 N0.getOperand(0).getValueType(),
2592 N0.getOperand(0), N1.getOperand(0));
2594 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2595 ORNode, N0.getOperand(1));
2605 if ((N0.getOpcode() == ISD::BITCAST ||
2606 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2608 SDValue In0 = N0.getOperand(0);
2617 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2635 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2636 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2639 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
2648 SDValue ShOp = N0->getOperand(1);
2662 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2664 N0->getOperand(0), N1->getOperand(0));
2672 ShOp = N0->getOperand(0);
2683 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
2685 N0->getOperand(1), N1->getOperand(1));
2700 SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1,
2705 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2709 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2717 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2724 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2731 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2744 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
2762 getSetCCResultType(N0.getSimpleValueType())))))
2763 return DAG.getSetCC(SDLoc(LocReference), N0.getValueType(),
2768 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2770 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2780 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2784 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
2785 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2786 CombineTo(N0.getNode(), NewAdd);
2800 SDValue N0 = N->getOperand(0);
2810 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2811 // do not return N0, because undef node may exist in N0
2814 N0.getValueType().getScalarType().getSizeInBits()),
2815 N0.getValueType());
2824 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2827 return N0;
2831 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2836 if (isConstantIntBuildVectorOrConstantInt(N0) &&
2838 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2841 return N0;
2848 if (SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1))
2851 if (N1C && N0.getOpcode() == ISD::OR)
2852 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2856 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2857 SDValue N0Op0 = N0.getOperand(0);
2862 N0.getValueType(), N0Op0);
2870 CombineTo(N0.getNode(), Zext);
2880 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2881 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2882 N0.getOpcode() == ISD::LOAD) {
2883 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2884 N0 : N0.getOperand(0) );
2973 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0
2982 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2983 (N0.getOpcode() == ISD::ANY_EXTEND &&
2984 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2985 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2987 ? cast<LoadSDNode>(N0.getOperand(0))
2988 : cast<LoadSDNode>(N0);
2990 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
3049 if (SDValue Combined = visitANDLike(N0, N1, N))
3053 if (N0.getOpcode() == N1.getOpcode()) {
3065 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
3066 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3075 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
3079 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3084 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3085 N0.hasOneUse()) {
3086 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3095 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
3099 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3104 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3105 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
3106 N0.getOperand(1), false);
3115 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
3129 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3130 std::swap(N0, N1);
3132 std::swap(N0, N1);
3133 if (N0.getOpcode() == ISD::AND) {
3134 if (!N0.getNode()->hasOneUse())
3136 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3139 N0 = N0.getOperand(0);
3153 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3154 std::swap(N0, N1);
3155 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3157 if (!N0.getNode()->hasOneUse() ||
3161 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3169 SDValue N00 = N0->getOperand(0);
3248 SDValue N0 = N.getOperand(0);
3253 if (N0.getOpcode() != ISD::SRL)
3255 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3261 if (N0.getOpcode() != ISD::SHL)
3263 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3288 Parts[Num] = N0.getOperand(0).getNode();
3298 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3311 if (N0.getOpcode() != ISD::OR)
3313 SDValue N00 = N0.getOperand(0);
3314 SDValue N01 = N0.getOperand(1);
3370 SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *LocReference) {
3374 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3380 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3417 getSetCCResultType(N0.getValueType())))))
3418 return DAG.getSetCC(SDLoc(LocReference), N0.getValueType(),
3424 if (N0.getOpcode() == ISD::AND &&
3426 N0.getOperand(1).getOpcode() == ISD::Constant &&
3429 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3433 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3437 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3439 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3440 N0.getOperand(0), N1.getOperand(0));
3447 if (N0.getOpcode() == ISD::AND &&
3449 N0.getOperand(0) == N1.getOperand(0) &&
3451 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3452 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3453 N0.getOperand(1), N1.getOperand(1));
3454 return DAG.getNode(ISD::AND, SDLoc(LocReference), VT, N0.getOperand(0), X);
3461 SDValue N0 = N->getOperand(0);
3471 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3474 return N0;
3477 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3478 // do not return N0, because undef node may exist in N0
3481 N0.getValueType().getScalarType().getSizeInBits()),
3482 N0.getValueType());
3493 if (isa<ShuffleVectorSDNode>(N0) &&
3497 N0->getOperand(1) == N1->getOperand(1) &&
3498 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3501 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
3504 // - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
3507 // and N0 as the second operand.
3538 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
3542 N0->getOperand(0), &Mask2[0]);
3548 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3553 if (isConstantIntBuildVectorOrConstantInt(N0) &&
3555 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3558 return N0;
3563 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3566 if (SDValue Combined = visitORLike(N0, N1, N))
3570 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3573 BSwap = MatchBSwapHWordLow(N, N0, N1);
3578 if (SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1))
3582 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3583 isa<ConstantSDNode>(N0.getOperand(1))) {
3584 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3589 DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1), COR);
3594 if (N0.getOpcode() == N1.getOpcode()) {
3600 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3866 SDValue N0 = N->getOperand(0);
3868 EVT VT = N0.getValueType();
3876 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3879 return N0;
3883 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3886 if (N0.getOpcode() == ISD::UNDEF)
3887 return N0;
3891 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3896 if (isConstantIntBuildVectorOrConstantInt(N0) &&
3898 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3901 return N0;
3903 if (SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1))
3908 if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3915 switch (N0.getOpcode()) {
3921 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
3922 N0.getOperand(3), NotCC);
3928 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3929 N0.getNode()->hasOneUse() &&
3930 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3931 SDValue V = N0.getOperand(0);
3932 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3940 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3941 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3943 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3952 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3953 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3955 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3963 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3964 N0->getOperand(1) == N1) {
3965 SDValue X = N0->getOperand(0);
3971 if (N1C && N0.getOpcode() == ISD::XOR) {
3972 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3973 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3975 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3979 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3984 if (N0 == N1)
4007 if (N0.getOpcode() == ISD::SHL)
4008 if (auto *ShlLHS = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
4011 N0.getOperand(1));
4014 if (N0.getOpcode() == N1.getOpcode()) {
4141 SDValue N0 = N->getOperand(0);
4143 EVT VT = N0.getValueType();
4156 if (N0.getOpcode() == ISD::AND) {
4157 SDValue N00 = N0->getOperand(0);
4158 SDValue N01 = N0->getOperand(1);
4174 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4179 return N0;
4185 return N0;
4187 if (N0.getOpcode() == ISD::UNDEF)
4198 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4205 if (N1C && N0.getOpcode() == ISD::SHL) {
4206 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4211 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4221 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4222 N0.getOpcode() == ISD::ANY_EXTEND ||
4223 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4224 N0.getOperand(0).getOpcode() == ISD::SHL) {
4225 SDValue N0Op0 = N0.getOperand(0);
4234 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
4235 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
4245 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4246 N0.getOperand(0).getOpcode() == ISD::SRL) {
4247 SDValue N0Op0 = N0.getOperand(0);
4253 SDValue NewOp0 = N0.getOperand(0);
4258 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4268 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4269 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4277 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4281 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4284 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
4290 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4295 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4303 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
4304 (isa<ConstantSDNode>(N0.getOperand(1)) ||
4305 isConstantSplatVector(N0.getOperand(1).getNode(), Val))) {
4306 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
4307 SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
4321 SDValue N0 = N->getOperand(0);
4323 EVT VT = N0.getValueType();
4336 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4341 return N0;
4344 return N0;
4350 return N0;
4353 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4362 N0.getOperand(0), DAG.getValueType(ExtVT));
4366 if (N1C && N0.getOpcode() == ISD::SRA) {
4367 if (ConstantSDNode *C1 = isConstOrConstSplat(N0.getOperand(1))) {
4371 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
4381 if (N0.getOpcode() == ISD::SHL && N1C) {
4383 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
4405 getShiftAmountTy(N0.getOperand(0).getValueType()));
4406 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
4407 N0.getOperand(0), Amt);
4408 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
4421 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4426 if (N0.getOpcode() == ISD::TRUNCATE &&
4427 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4428 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4429 N0.getOperand(0).hasOneUse() &&
4430 N0.getOperand(0).getOperand(1).hasOneUse() &&
4432 SDValue N0Op0 = N0.getOperand(0);
4454 if (DAG.SignBitIsZero(N0))
4455 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4467 SDValue N0 = N->getOperand(0);
4469 EVT VT = N0.getValueType();
4482 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4487 return N0;
4493 return N0;
4500 if (N1C && N0.getOpcode() == ISD::SRL) {
4501 if (ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1))) {
4506 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4512 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4513 N0.getOperand(0).getOpcode() == ISD::SRL &&
4514 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4516 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4518 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4519 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4525 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
4526 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
4527 N0.getOperand(0)->getOperand(0),
4533 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4534 unsigned BitSize = N0.getScalarValueSizeInBits();
4537 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4543 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4545 EVT SmallVT = N0.getOperand(0).getValueType();
4552 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
4553 N0.getOperand(0),
4566 if (N0.getOpcode() == ISD::SRA)
4567 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4571 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4574 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
4592 SDValue Op = N0.getOperand(0);
4595 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4610 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4662 SDValue N0 = N->getOperand(0);
4666 if (isa<ConstantSDNode>(N0))
4667 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4672 SDValue N0 = N->getOperand(0);
4676 if (isa<ConstantSDNode>(N0))
4677 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4682 SDValue N0 = N->getOperand(0);
4686 if (isa<ConstantSDNode>(N0))
4687 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4692 SDValue N0 = N->getOperand(0);
4696 if (isa<ConstantSDNode>(N0))
4697 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4702 SDValue N0 = N->getOperand(0);
4706 if (isa<ConstantSDNode>(N0))
4707 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4749 SDValue N0 = N->getOperand(0);
4753 EVT VT0 = N0.getValueType();
4759 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4768 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4789 N0, DAG.getConstant(1, VT0));
4790 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4791 N0, DAG.getConstant(1, VT0));
4799 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4805 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4811 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4814 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4815 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4818 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4819 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4826 if (N0.getOpcode() == ISD::SETCC) {
4838 VT.isFloatingPoint() && N0.hasOneUse() &&
4840 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4843 combineMinNumMaxNum(SDLoc(N), VT, N0.getOperand(0), N0.getOperand(1),
4853 N0.getOperand(0), N0.getOperand(1),
4854 N1, N2, N0.getOperand(2));
4855 return SimplifySelect(SDLoc(N), N0, N1, N2);
4862 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
4863 SDValue Cond0 = N0->getOperand(0);
4864 SDValue Cond1 = N0->getOperand(1);
4871 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
4872 SDValue Cond0 = N0->getOperand(0);
4873 SDValue Cond1 = N0->getOperand(1);
4886 if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) {
4889 SDValue And = DAG.getNode(ISD::AND, SDLoc(N), N0.getValueType(),
4890 N0, N1_0);
4895 if (SDValue Combined = visitANDLike(N0, N1_0, N))
4905 if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) {
4908 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N), N0.getValueType(),
4909 N0, N2_0);
4914 if (SDValue Combined = visitORLike(N0, N2_0, N))
5157 SDValue N0 = N->getOperand(0);
5167 if (N0.getOpcode() == ISD::SETCC) {
5168 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
5169 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5197 if (N0.getOpcode() == ISD::SETCC) {
5206 std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
5222 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5225 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5233 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
5243 SDValue N0 = N->getOperand(0);
5255 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
5256 N0, N1, CC, SDLoc(N), false);
5282 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
5301 SDValue N0 = N->getOperand(0);
5310 if (isa<ConstantSDNode>(N0))
5311 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
5319 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
5324 unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
5327 unsigned NumElts = N0->getNumOperands();
5331 SDValue Op = N0->getOperand(i);
5354 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
5359 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
5360 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
5361 UE = N0.getNode()->use_end();
5366 if (UI.getUse().getResNo() != N0.getResNo())
5377 if (UseOp == N0)
5437 SDValue N0 = N->getOperand(0);
5439 EVT SrcVT = N0.getValueType();
5462 if (N0->getOpcode() != ISD::LOAD)
5465 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5468 !N0.hasOneUse() || LN0->isVolatile() || !DstVT.isVector() ||
5473 if (!ExtendUsesToFormExtLoad(N, N0, N->getOpcode(), SetCCs, TLI))
5524 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), NewValue);
5525 CombineTo(N0.getNode(), Trunc, NewChain);
5532 SDValue N0 = N->getOperand(0);
5541 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5543 N0.getOperand(0));
5545 if (N0.getOpcode() == ISD::TRUNCATE) {
5548 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5550 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5551 if (NarrowLoad.getNode() != N0.getNode()) {
5552 CombineTo(N0.getNode(), NarrowLoad);
5561 SDValue Op = N0.getOperand(0);
5563 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
5586 N0.getValueType())) {
5588 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
5590 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
5592 DAG.getValueType(N0.getValueType()));
5599 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5601 !cast<LoadSDNode>(N0)->isVolatile()) ||
5602 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()))) {
5605 if (!N0.hasOneUse())
5606 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
5610 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5613 LN0->getBasePtr(), N0.getValueType(),
5616 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5617 N0.getValueType(), ExtLoad);
5618 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5632 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5633 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5634 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5643 CombineTo(N0.getNode(),
5644 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5645 N0.getValueType(), ExtLoad),
5653 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5654 N0.getOpcode() == ISD::XOR) &&
5655 isa<LoadSDNode>(N0.getOperand(0)) &&
5656 N0.getOperand(1).getOpcode() == ISD::Constant &&
5657 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()) &&
5658 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5659 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5663 if (!N0.hasOneUse())
5664 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
5671 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5673 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5676 SDLoc(N0.getOperand(0)),
5677 N0.getOperand(0).getValueType(), ExtLoad);
5679 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5687 if (N0.getOpcode() == ISD::SETCC) {
5688 EVT N0VT = N0.getOperand(0).getValueType();
5705 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5706 N0.getOperand(1),
5707 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5715 N0.getOperand(0), N0.getOperand(1),
5716 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5726 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5728 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5732 EVT SetCCVT = getSetCCResultType(N0.getOperand(0).getValueType());
5735 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5737 N0.getOperand(0), N0.getOperand(1), CC);
5746 DAG.SignBitIsZero(N0))
5747 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
5791 SDValue N0 = N->getOperand(0);
5800 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5802 N0.getOperand(0));
5810 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
5812 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
5815 N0.getValueSizeInBits(),
5830 if (N0.getOpcode() == ISD::TRUNCATE) {
5831 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5833 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5834 if (NarrowLoad.getNode() != N0.getNode()) {
5835 CombineTo(N0.getNode(), NarrowLoad);
5844 if (N0.getOpcode() == ISD::TRUNCATE &&
5849 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5851 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5852 if (NarrowLoad.getNode() != N0.getNode()) {
5853 CombineTo(N0.getNode(), NarrowLoad);
5860 SDValue Op = N0.getOperand(0);
5869 N0.getValueType().getScalarType());
5874 if (N0.getOpcode() == ISD::AND &&
5875 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5876 N0.getOperand(1).getOpcode() == ISD::Constant &&
5877 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5878 N0.getValueType()) ||
5879 !TLI.isZExtFree(N0.getValueType(), VT))) {
5880 SDValue X = N0.getOperand(0).getOperand(0);
5886 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5895 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5897 !cast<LoadSDNode>(N0)->isVolatile()) ||
5898 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()))) {
5901 if (!N0.hasOneUse())
5902 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
5906 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5909 LN0->getBasePtr(), N0.getValueType(),
5912 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5913 N0.getValueType(), ExtLoad);
5914 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5929 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5930 N0.getOpcode() == ISD::XOR) &&
5931 isa<LoadSDNode>(N0.getOperand(0)) &&
5932 N0.getOperand(1).getOpcode() == ISD::Constant &&
5933 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&
5934 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5935 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5939 if (!N0.hasOneUse())
5940 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
5947 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5949 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5952 SDLoc(N0.getOperand(0)),
5953 N0.getOperand(0).getValueType(), ExtLoad);
5955 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5965 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5966 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5967 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5976 CombineTo(N0.getNode(),
5977 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
5984 if (N0.getOpcode() == ISD::SETCC) {
5986 N0.getValueType().getVectorElementType() == MVT::i1) {
5987 EVT N0VT = N0.getOperand(0).getValueType();
5988 if (getSetCCResultType(N0VT) == N0.getValueType())
6003 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
6004 N0.getOperand(1),
6005 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
6019 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
6020 N0.getOperand(1),
6021 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6029 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
6031 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6036 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
6037 isa<ConstantSDNode>(N0.getOperand(1)) &&
6038 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
6039 N0.hasOneUse()) {
6040 SDValue ShAmt = N0.getOperand(1);
6042 if (N0.getOpcode() == ISD::SHL) {
6043 SDValue InnerZExt = N0.getOperand(0);
6058 return DAG.getNode(N0.getOpcode(), DL, VT,
6059 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
6067 SDValue N0 = N->getOperand(0);
6077 if (N0.getOpcode() == ISD::ANY_EXTEND ||
6078 N0.getOpcode() == ISD::ZERO_EXTEND ||
6079 N0.getOpcode() == ISD::SIGN_EXTEND)
6080 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
6084 if (N0.getOpcode() == ISD::TRUNCATE) {
6085 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
6087 SDNode* oye = N0.getNode()->getOperand(0).getNode();
6088 if (NarrowLoad.getNode() != N0.getNode()) {
6089 CombineTo(N0.getNode(), NarrowLoad);
6098 if (N0.getOpcode() == ISD::TRUNCATE) {
6099 SDValue TruncOp = N0.getOperand(0);
6109 if (N0.getOpcode() == ISD::AND &&
6110 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
6111 N0.getOperand(1).getOpcode() == ISD::Constant &&
6112 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
6113 N0.getValueType())) {
6114 SDValue X = N0.getOperand(0).getOperand(0);
6120 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6130 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
6131 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6132 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
6135 if (!N0.hasOneUse())
6136 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
6138 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6141 LN0->getBasePtr(), N0.getValueType(),
6144 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6145 N0.getValueType(), ExtLoad);
6146 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
6156 if (N0.getOpcode() == ISD::LOAD &&
6157 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6158 N0.hasOneUse()) {
6159 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6167 CombineTo(N0.getNode(),
6168 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6169 N0.getValueType(), ExtLoad),
6175 if (N0.getOpcode() == ISD::SETCC) {
6182 EVT N0VT = N0.getOperand(0).getValueType();
6189 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
6190 N0.getOperand(1),
6191 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6198 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
6199 N0.getOperand(1),
6200 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6207 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
6209 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6269 SDValue N0 = N->getOperand(0);
6285 N0 = SDValue(N, 0);
6286 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
6302 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
6303 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6307 N0 = N0.getOperand(0);
6309 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
6314 if (!isa<LoadSDNode>(N0)) return SDValue();
6319 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
6325 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
6333 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
6334 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
6335 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6337 N0 = N0.getOperand(0);
6343 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
6347 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6373 EVT PtrType = N0.getOperand(1).getValueType();
6396 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
6401 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
6408 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6423 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
6432 SDValue N0 = N->getOperand(0);
6440 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
6441 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
6444 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
6445 return N0;
6448 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
6449 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
6451 N0.getOperand(0), N1);
6456 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
6457 SDValue N00 = N0.getOperand(0);
6464 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
6465 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
6481 if (N0.getOpcode() == ISD::SRL) {
6482 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
6486 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
6489 N0.getOperand(0), N0.getOperand(1));
6494 if (ISD::isEXTLoad(N0.getNode()) &&
6495 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6496 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6497 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6499 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6505 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6510 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6511 N0.hasOneUse() &&
6512 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6513 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6515 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6521 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6526 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
6527 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
6528 N0.getOperand(1), false);
6536 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
6538 unsigned NumElts = N0->getNumOperands();
6542 SDValue Op = N0->getOperand(i);
6561 SDValue N0 = N->getOperand(0);
6566 if (N0.getValueType() == N->getValueType(0))
6567 return N0;
6569 if (isConstantIntBuildVectorOrConstantInt(N0))
6570 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
6572 if (N0.getOpcode() == ISD::TRUNCATE)
6573 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6575 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
6576 N0.getOpcode() == ISD::SIGN_EXTEND ||
6577 N0.getOpcode() == ISD::ANY_EXTEND) {
6578 if (N0.getOperand(0).getValueType().bitsLT(VT))
6580 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
6581 N0.getOperand(0));
6582 if (N0.getOperand(0).getValueType().bitsGT(VT))
6584 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6587 return N0.getOperand(0);
6600 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6601 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
6603 EVT VecTy = N0.getOperand(0).getValueType();
6604 EVT ExTy = N0.getValueType();
6613 SDValue EltNo = N0->getOperand(1);
6620 NVT, N0.getOperand(0));
6629 if (N0.getOpcode() == ISD::SELECT) {
6630 EVT SrcVT = N0.getValueType();
6633 SDLoc SL(N0);
6634 SDValue Cond = N0.getOperand(0);
6635 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
6636 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
6646 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
6647 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
6648 N0.getOperand(0).hasOneUse()) {
6650 SDValue BuildVect = N0.getOperand(0);
6679 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
6686 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
6692 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
6693 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6700 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
6707 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
6713 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
6714 SDValue X = N0.getOperand(i);
6796 SDValue N0 = N->getOperand(0);
6804 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
6806 bool isSimple = cast<BuildVectorSDNode>(N0)->isConstant();
6812 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
6816 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
6821 (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() &&
6823 (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() &&
6825 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
6829 if (N0.getOpcode() == ISD::BITCAST)
6831 N0.getOperand(0));
6835 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6837 !cast<LoadSDNode>(N0)->isVolatile() &&
6839 TLI.hasBigEndianPartOrdering(N0.getValueType()) ==
6842 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
6843 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6854 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6862 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
6863 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
6864 N0.getNode()->hasOneUse() && VT.isInteger() &&
6865 !VT.isVector() && !N0.getValueType().isVector()) {
6866 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
6867 N0.getOperand(0));
6871 if (N0.getOpcode() == ISD::FNEG)
6874 assert(N0.getOpcode() == ISD::FABS);
6883 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
6884 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
6886 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
6889 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6890 IntXVT, N0.getOperand(1));
6914 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6915 VT, N0.getOperand(0));
6925 if (N0.getOpcode() == ISD::BUILD_PAIR) {
6926 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
7068 SDValue N0 = N->getOperand(0);
7073 if (N0.getOpcode() == ISD::FMUL &&
7074 (Aggressive || N0->hasOneUse())) {
7076 N0.getOperand(0), N0.getOperand(1), N1);
7084 N1.getOperand(0), N1.getOperand(1), N0);
7090 if (N0.getOpcode() == ISD::FMA &&
7091 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7093 N0.getOperand(0), N0.getOperand(1),
7095 N0.getOperand(2).getOperand(0),
7096 N0.getOperand(2).getOperand(1),
7108 N0));
7120 SDValue N0 = N->getOperand(0);
7127 if (N0.getOpcode() == ISD::FMUL &&
7128 (Aggressive || N0->hasOneUse())) {
7130 N0.getOperand(0), N0.getOperand(1),
7141 N1.getOperand(1), N0);
7144 if (N0.getOpcode() == ISD::FNEG &&
7145 N0.getOperand(0).getOpcode() == ISD::FMUL &&
7146 (Aggressive || (N0->hasOneUse() && N0.getOperand(0).hasOneUse()))) {
7147 SDValue N00 = N0.getOperand(0).getOperand(0);
7148 SDValue N01 = N0.getOperand(0).getOperand(1);
7158 if (N0.getOpcode() == FusedOpcode &&
7159 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7161 N0.getOperand(0), N0.getOperand(1),
7163 N0.getOperand(2).getOperand(0),
7164 N0.getOperand(2).getOperand(1),
7182 N21, N0));
7190 SDValue N0 = N->getOperand(0);
7192 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7204 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
7208 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
7213 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
7218 isNegatibleForFree(N0, LegalOperations, TLI, &Options) == 2)
7220 GetNegatedExpression(N0, DAG, LegalOperations));
7230 return N0;
7233 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
7234 isa<ConstantFPSDNode>(N0.getOperand(1)))
7235 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
7237 N0.getOperand(1), N1));
7240 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
7244 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
7251 if (N0.getOpcode() == ISD::FMUL) {
7252 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
7253 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
7256 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
7266 N0.getOperand(0) == N1.getOperand(0)) {
7271 N0.getOperand(0), NewCFP);
7280 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
7284 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, NewCFP);
7288 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
7289 N0.getOperand(0) == N0.getOperand(1) &&
7290 N1.getOperand(0) == N0.getOperand(0)) {
7298 if (N0.getOpcode() == ISD::FADD && AllowNewConst) {
7299 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
7301 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
7302 (N0.getOperand(0) == N1))
7311 N1.getOperand(0) == N0)
7313 N0, DAG.getConstantFP(3.0, VT));
7318 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
7319 N0.getOperand(0) == N0.getOperand(1) &&
7321 N0.getOperand(0) == N1.getOperand(0))
7323 N0.getOperand(0), DAG.getConstantFP(4.0, VT));
7354 if (N0.getOpcode() == ISD::FP_EXTEND) {
7355 SDValue N00 = N0.getOperand(0);
7373 N10.getOperand(1)), N0);
7382 SDValue N0 = N->getOperand(0);
7384 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
7397 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
7401 return DAG.getNode(ISD::FADD, dl, VT, N0,
7408 return N0;
7419 if (N0 == N1)
7428 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, &Options))
7431 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, &Options))
7464 if (N0.getOpcode() == ISD::FP_EXTEND) {
7465 SDValue N00 = N0.getOperand(0);
7487 N0);
7492 if (N0.getOpcode() == ISD::FP_EXTEND) {
7493 SDValue N00 = N0.getOperand(0);
7510 if (N0.getOpcode() == ISD::FNEG) {
7511 SDValue N00 = N0.getOperand(0);
7532 SDValue N0 = N->getOperand(0);
7534 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
7548 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
7551 if (isConstantFPBuildVectorOrConstantFP(N0) &&
7553 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
7557 return N0;
7565 if (N0.getOpcode() == ISD::FMUL) {
7569 SDValue N00 = N0.getOperand(0);
7570 SDValue N01 = N0.getOperand(1);
7593 if (N0.getOpcode() == ISD::FADD && N0.getOperand(0) == N0.getOperand(1)) {
7597 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), MulConsts);
7603 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
7608 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
7611 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
7617 GetNegatedExpression(N0, DAG, LegalOperations),
7626 SDValue N0 = N->getOperand(0);
7629 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7636 if (isa<ConstantFPSDNode>(N0) &&
7639 return DAG.getNode(ISD::FMA, dl, VT, N0, N1, N2);
7651 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
7655 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
7660 N0 == N2.getOperand(0) &&
7662 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7669 N0.getOpcode() == ISD::FMUL && N1CFP &&
7670 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
7672 N0.getOperand(0),
7673 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
7681 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
7685 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
7692 if (Options.UnsafeFPMath && N1CFP && N0 == N2)
7693 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7699 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
7700 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7709 SDValue N0 = N->getOperand(0);
7711 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7724 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
7742 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
7750 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7757 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7764 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7784 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7792 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7797 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
7803 GetNegatedExpression(N0, DAG, LegalOperations),
7850 SDValue N0 = N->getOperand(0);
7852 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7858 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
7890 SDValue N0 = N->getOperand(0);
7892 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7897 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
7905 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7909 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
7916 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
7917 N0.getOpcode() == ISD::FCOPYSIGN)
7919 N0.getOperand(0), N1);
7923 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7928 N0, N1.getOperand(1));
7934 N0, N1.getOperand(0));
7940 SDValue N0 = N->getOperand(0);
7942 EVT OpVT = N0.getValueType();
7945 if (isConstantIntBuildVectorOrConstantInt(N0) &&
7949 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7956 if (DAG.SignBitIsZero(N0))
7957 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7963 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
7968 { N0.getOperand(0), N0.getOperand(1),
7970 N0.getOperand(2) };
7976 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
7977 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
7981 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
7983 N0.getOperand(0).getOperand(2) };
7992 SDValue N0 = N->getOperand(0);
7994 EVT OpVT = N0.getValueType();
7997 if (isConstantIntBuildVectorOrConstantInt(N0) &&
8001 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
8008 if (DAG.SignBitIsZero(N0))
8009 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
8016 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
8020 { N0.getOperand(0), N0.getOperand(1),
8022 N0.getOperand(2) };
8032 SDValue N0 = N->getOperand(0);
8035 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
8038 SDValue Src = N0.getOperand(0);
8040 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP;
8055 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(N0.getValueType());
8075 SDValue N0 = N->getOperand(0);
8076 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8081 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
8087 SDValue N0 = N->getOperand(0);
8088 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8093 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
8099 SDValue N0 = N->getOperand(0);
8101 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8106 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
8109 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
8110 return N0.getOperand(0);
8113 if (N0.getOpcode() == ISD::FP_ROUND) {
8115 const bool N0IsTrunc = N0.getNode()->getConstantOperandVal(1) == 1;
8122 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
8127 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
8128 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
8129 N0.getOperand(0), N1);
8132 Tmp, N0.getOperand(1));
8139 SDValue N0 = N->getOperand(0);
8142 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8154 SDValue N0 = N->getOperand(0);
8163 if (isConstantFPBuildVectorOrConstantFP(N0))
8164 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
8167 if (N0.getOpcode() == ISD::FP16_TO_FP &&
8169 return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0));
8173 if (N0.getOpcode() == ISD::FP_ROUND
8174 && N0.getNode()->getConstantOperandVal(1) == 1) {
8175 SDValue In = N0.getOperand(0);
8179 In, N0.getOperand(1));
8184 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
8185 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
8186 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
8189 LN0->getBasePtr(), N0.getValueType(),
8192 CombineTo(N0.getNode(),
8193 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
8194 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
8203 SDValue N0 = N->getOperand(0);
8207 if (isConstantFPBuildVectorOrConstantFP(N0))
8208 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
8214 SDValue N0 = N->getOperand(0);
8218 if (isConstantFPBuildVectorOrConstantFP(N0))
8219 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
8225 SDValue N0 = N->getOperand(0);
8229 if (isConstantFPBuildVectorOrConstantFP(N0))
8230 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
8237 SDValue N0 = N->getOperand(0);
8241 if (isConstantFPBuildVectorOrConstantFP(N0))
8242 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
8244 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
8246 return GetNegatedExpression(N0, DAG, LegalOperations);
8251 N0.getOpcode() == ISD::BITCAST &&
8252 N0.getNode()->hasOneUse()) {
8253 SDValue Int = N0.getOperand(0);
8257 if (N0.getValueType().isVector()) {
8260 SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
8266 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
8274 if (N0.getOpcode() == ISD::FMUL) {
8275 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
8283 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
8284 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)));
8292 SDValue N0 = N->getOperand(0);
8294 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8306 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0);
8313 SDValue N0 = N->getOperand(0);
8315 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8327 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0);
8334 SDValue N0 = N->getOperand(0);
8338 if (isConstantFPBuildVectorOrConstantFP(N0))
8339 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
8342 if (N0.getOpcode() == ISD::FABS)
8347 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
8348 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
8353 N0.getOpcode() == ISD::BITCAST &&
8354 N0.getNode()->hasOneUse()) {
8355 SDValue Int = N0.getOperand(0);
8359 if (N0.getValueType().isVector()) {
8362 SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
8368 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
9828 SDValue N0 = Value.getOperand(0);
9829 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
9830 Chain == SDValue(N0.getNode(), 1)) {
9831 LoadSDNode *LD = cast<LoadSDNode>(N0);
9885 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
9902 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
11850 static SDValue simplifyShuffleOperands(ShuffleVectorSDNode *SVN, SDValue N0,
11861 SDValue S0 = simplifyShuffleOperandRecursively(N0UsedElements, N0, DAG);
11863 if (S0 == N0 && S1 == N1)
11875 SDValue N0 = N->getOperand(0);
11880 EVT ConcatVT = N0.getOperand(0).getValueType();
11890 N0 = DAG.getVectorShuffle(ConcatVT, SDLoc(N), N0.getOperand(0), N0.getOperand(1),
11893 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, N0, N1);
11918 if (FirstElt < N0.getNumOperands())
11919 Ops.push_back(N0.getOperand(FirstElt));
11921 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
11924 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
11937 SDValue N0 = N->getOperand(0);
11940 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
11943 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
11949 if (N0 == N1) {
11956 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
11961 if (N0.getOpcode() == ISD::UNDEF) {
11990 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
11996 SDNode *V = N0.getNode();
12021 return N0;
12030 return N0;
12049 if (SDValue S = simplifyShuffleOperands(SVN, N0, N1, DAG))
12052 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
12056 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
12071 SDValue &S = (M < (int)NumElts ? N0 : N1);
12103 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
12108 SDValue BC0 = N0;
12180 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
12189 bool HasSameOp0 = N0 == SV0;
12191 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
12203 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && N->isOnlyUserOf(N0.getNode()) &&
12205 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
12226 // This shuffle index refers to the inner shuffle N0. Lookup the inner
12333 SDValue N0 = N->getOperand(0);
12338 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
12339 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
12347 N->getOperand(1), N0.getOperand(1));
12353 N0.getOperand(0), N->getOperand(1));
12360 SDValue N0 = N->getOperand(0);
12363 if (N0->getOpcode() == ISD::FP16_TO_FP)
12364 return N0->getOperand(0);
12512 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
12514 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
12516 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
12517 cast<CondCodeSDNode>(N0.getOperand(2))->get());
12526 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
12527 N0.getValueType(),
12659 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
12661 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
12673 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
12674 N0, N1, CC, DL, false);
12691 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
12693 return DAG.getNode(ISD::FABS, DL, VT, N0);
12697 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
12741 getSetCCResultType(N0.getValueType()),
12742 N0, N1, CC);
12761 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
12762 EVT XType = N0.getValueType();
12771 getShiftAmountTy(N0.getValueType()));
12772 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
12773 XType, N0, ShCt);
12784 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
12785 XType, N0,
12787 getShiftAmountTy(N0.getValueType())));
12805 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
12806 N0->getValueType(0) == VT &&
12809 SDValue AndLHS = N0->getOperand(0);
12810 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
12817 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
12824 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
12832 TLI.getBooleanContents(N0.getValueType()) ==
12844 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
12848 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
12849 N0, N1, CC);
12857 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
12880 EVT XType = N0.getValueType();
12883 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
12893 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
12900 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
12901 XType, DAG.getConstant(0, XType), N0);
12902 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType);
12910 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
12912 getShiftAmountTy(N0.getValueType())));
12927 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
12931 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
12934 EVT XType = N0.getValueType();
12936 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
12937 N0,
12939 getShiftAmountTy(N0.getValueType())));
12940 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
12941 XType, N0, Shift);
12952 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
12957 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
