Lines Matching defs:N0
1830 SDNode *N0 = N->getOperand(0).getNode();
1832 return N0->hasOneUse() && N1->hasOneUse() &&
1833 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1841 SDNode *N0 = N->getOperand(0).getNode();
1843 return N0->hasOneUse() && N1->hasOneUse() &&
1844 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1855 SDNode *N0 = Op.getOperand(0).getNode();
1859 bool isN0SExt = isSignExtended(N0, DAG);
1864 bool isN0ZExt = isZeroExtended(N0, DAG);
1871 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1874 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1878 std::swap(N0, N1);
1899 Op0 = skipExtensionForVectorMULL(N0, DAG);
1908 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1909 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1911 return DAG.getNode(N0->getOpcode(), DL, VT,
6888 SDValue N0 = N->getOperand(0);
6895 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6896 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6900 N0.getOperand(0));
6904 N0.getOperand(0), DAG.getConstant(0, VT));
6905 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6933 SDValue N0 = N->getOperand(0);
6938 // Add (N0 < 0) ? Pow2 - 1 : 0;
6940 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6941 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6942 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7087 SDValue N0 = N->getOperand(0);
7088 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7090 !cast<LoadSDNode>(N0)->isVolatile()) {
7091 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7182 SDValue N0 = N->getOperand(0);
7183 if (N0.getOpcode() != ISD::AND)
7196 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7214 N0->getOperand(1 - i), N1->getOperand(1 - j));
7313 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7327 N0->getOpcode() == ISD::TRUNCATE &&
7329 SDValue N00 = N0->getOperand(0);
7356 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7358 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7385 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
8612 SDValue N0 = N->getOperand(0);
8613 EVT CCVT = N0.getValueType();
8615 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8620 EVT CmpVT = N0.getOperand(0).getValueType();
8630 N0.getOperand(0), N0.getOperand(1),
8631 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8641 SDValue N0 = N->getOperand(0);
8644 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8650 EVT SrcVT = N0.getOperand(0).getValueType();
8666 SDLoc DL(N0);
8668 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8670 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8671 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
