Lines Matching defs:Size
1380 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1616 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1747 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1750 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1754 // Must extend size to at least 64 bits to be used as an operand for VMULL.
2069 unsigned NumArgs = Ins.size();
2093 assert(ArgLocs.size() == Ins.size());
2095 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2102 int Size = Ins[i].Flags.getByValSize();
2103 unsigned NumRegs = (Size + 7) / 8;
2143 // truncate to the right size.
2337 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2438 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2456 if (RVLocs1.size() != RVLocs2.size())
2458 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2582 unsigned NumArgs = Outs.size();
2600 unsigned NumArgs = Outs.size();
2641 // popped size 16-byte aligned.
2669 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2783 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2842 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2921 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
3132 // Different choices can be made for the maximum size of the TLS area for a
3133 // module. For the small address model, the default TLS size is 16MiB and the
3134 // maximum TLS size is 4GiB.
3135 // FIXME: add -mtls-size command line option and make it control the 16MiB
4225 // w - An FP/SIMD register of some size in the range v0-v31
4226 // x - An FP/SIMD register of some size in the range v0-v15
4239 // register name, whatever the size of the variable, unless the asm operand
4248 if (Constraint.size() == 1) {
4300 if (Constraint.size() == 1) {
4332 unsigned Size = Constraint.size();
4333 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4334 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4336 std::string(&Constraint[2], &Constraint[Size - 1]);
4582 if (Sources.size() > 2)
4585 // Find out the smallest element size among result and two sources, and use
4586 // it as element size to build the shuffle_vector.
4711 for (unsigned i = 0; i < Sources.size(); ++i)
4911 if (M.size() != static_cast<size_t>(NumInputElements))
5212 // to make a vector of the same size as this SHUFFLE. We can ignore the
5517 // particular size?
6128 unsigned Size = Op.getValueType().getSizeInBits();
6130 switch (Size) {
6149 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6704 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6714 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6720 if (Size >= 8 &&
6725 if (Size >= 4 &&
6892 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7338 for (size_t i = 0; i < Mask.size(); ++i)
7421 "unexpected vector size on extract_vector_elt!");
7880 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
8119 // If the increment is a constant, it must match the memory ref size.
8241 // If the increment is a constant, it must match the memory ref size.
8607 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8621 // Only combine when the result type is of the same size as the compared
8932 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8933 return Size == 128;
8940 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8941 return Size == 128;
8947 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
8948 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
