Lines Matching refs:SmallVectorImpl
2053 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2054 SmallVectorImpl<SDValue> &InVals) const {
2324 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2325 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2373 const SmallVectorImpl<ISD::OutputArg> &Outs,
2374 const SmallVectorImpl<SDValue> &OutVals,
2375 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2536 SmallVectorImpl<SDValue> &InVals) const {
2895 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2907 const SmallVectorImpl<ISD::OutputArg> &Outs,
2908 const SmallVectorImpl<SDValue> &OutVals,
6155 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
8873 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8891 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
