Home | History | Annotate | Download | only in AArch64

Lines Matching refs:dsub

3407       VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3409       VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3435     return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
4522   return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
6024       unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6141       return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
7276     if (idx != AArch64::dsub)
7278     // The dsub reference is equivalent to a lane zero subvector reference.
7301     SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);