Lines Matching full:b00
895 let Inst{20-19} = 0b00;
1276 let Inst{15-14} = 0b00;
2119 let Inst{11-10} = 0b00;
2348 let Inst{25-24} = 0b00;
2363 let Inst{25-24} = 0b00;
2460 let Inst{25-24} = 0b00;
2538 let Inst{25-24} = 0b00;
2610 let Inst{25-24} = 0b00;
2682 let Inst{25-24} = 0b00;
2754 let Inst{25-24} = 0b00;
2828 let Inst{25-24} = 0b00;
2881 let Inst{25-24} = 0b00;
2885 let Inst{11-10} = 0b00;
2940 let Inst{25-24} = 0b00;
3033 let Inst{25-24} = 0b00;
3408 let Inst{30-29} = 0b00;
3429 let Inst{30-29} = 0b00;
3443 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3449 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3470 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3479 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3671 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3676 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3681 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3686 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3729 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3737 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3741 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3745 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
4094 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4097 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4120 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4123 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4142 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
4146 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
4171 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4174 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4357 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4360 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4397 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4399 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4415 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4418 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4437 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4441 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4466 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4469 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4491 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4494 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4530 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4533 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4644 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4647 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4697 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4700 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4851 let Inst{11-10} = 0b00;
4877 let Inst{11-10} = 0b00;
5344 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5571 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5586 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5601 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5667 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5669 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5680 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5682 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5990 let Inst{11-10} = 0b00;
6011 let Inst{11-10} = 0b00;
6022 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
6030 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
6066 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
6074 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
7800 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
7812 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
7823 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
7843 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
7873 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
7885 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
7895 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
7915 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
8125 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
8127 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
8142 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
8145 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
8771 let Inst{11-10} = 0b00;
