Lines Matching full:b00
405 defm MOVN : MoveImmediate<0b00, "movn">;
656 defm LSLV : Shift<0b00, "lsl", shl>;
720 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
725 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
737 defm AND : LogicalImm<0b00, "and", and, "bic">;
754 defm AND : LogicalReg<0b00, 0, "and", and>;
755 defm BIC : LogicalReg<0b00, 1, "bic",
854 defm SBFM : BitfieldImm<0b00, "sbfm">;
964 defm CSEL : CondSelect<0, 0b00, "csel">;
968 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1117 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1121 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1136 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1138 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1145 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1147 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1154 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1156 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1164 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1166 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1175 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1181 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1185 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1192 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1193 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1353 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1365 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1449 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1492 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1496 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1521 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1523 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1542 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1554 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1563 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1703 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1707 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1744 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1751 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1752 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1761 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1765 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1772 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1773 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1776 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1786 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1790 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1797 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1798 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1801 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1813 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1815 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1820 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1822 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1827 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1829 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1834 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1836 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1844 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1845 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1846 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1847 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1851 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1852 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1853 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1854 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1855 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1945 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1948 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1951 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1954 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1957 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1960 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1963 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1965 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1969 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2044 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2047 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2050 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2053 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2056 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2059 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2062 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2065 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2068 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2157 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2158 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2160 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2161 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2165 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2166 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2167 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2168 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2169 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2170 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2171 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2173 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2174 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2219 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2220 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2221 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2222 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2223 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2224 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2225 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2227 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2228 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2277 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2282 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2287 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2292 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2297 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2302 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2321 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2327 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2335 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2336 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2339 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2340 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2552 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2617 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2648 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2800 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2807 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
4150 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4190 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4784 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4788 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4792 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4796 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4868 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4954 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4958 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4962 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
