Lines Matching defs:ARMBaseInstrInfo
1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
15 #include "ARMBaseInstrInfo.h"
94 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
108 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
118 ScheduleHazardRecognizer *ARMBaseInstrInfo::
127 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
277 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
368 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
397 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
435 bool ARMBaseInstrInfo::
442 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
458 bool ARMBaseInstrInfo::
480 bool ARMBaseInstrInfo::
507 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
561 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
600 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
683 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
694 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
715 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
737 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
869 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
880 void ARMBaseInstrInfo::
1017 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1065 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1071 void ARMBaseInstrInfo::
1208 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1256 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1263 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1388 void ARMBaseInstrInfo::
1417 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1432 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1527 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1608 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1638 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1681 bool ARMBaseInstrInfo::
1697 bool ARMBaseInstrInfo::
1722 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1758 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1819 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1841 ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1949 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
2102 const ARMBaseInstrInfo &TII) {
2244 bool ARMBaseInstrInfo::
2358 bool ARMBaseInstrInfo::
2606 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2967 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2977 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3121 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3162 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3197 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3237 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3266 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3613 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3702 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3918 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3936 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3986 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4004 bool ARMBaseInstrInfo::
4026 bool ARMBaseInstrInfo::
4041 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
4052 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4083 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4118 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4210 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4418 unsigned ARMBaseInstrInfo::
4480 void ARMBaseInstrInfo::
4515 bool ARMBaseInstrInfo::hasNOP() const {
4519 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4533 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4558 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4579 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
