Lines Matching full:dsrc
4229 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4236 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4256 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4257 // Note that DSrc has been widened and the other lane may be undef, which
4310 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4312 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4315 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4321 if (DSrc == DDst) {
4341 // job. It turns out that the VEXTs needed will only use DSrc once, with
4355 // On the first instruction, both DSrc and DDst may be <undef> if present.
4358 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4362 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4376 // it is not <undef>. DSrc, if present, can be <undef> as above.
4377 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4378 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4381 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4382 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
